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160AT R1509D DBUR0520 8N6011 2450BP 1N4005G USB2259 167BZC
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256Mb: x4, x8, x16 DDR2 SDRAM
DDR2 SDRAM
Features
* * * * * * * * * * * * * * VDD = +1.8V 0.1V, VDDQ = +1.8V 0.1V JEDEC standard 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option Four-bit prefetch architecture Duplicate output strobe (RDQS) option for x8 configuration DLL to align DQ and DQS transitions with CK Four internal banks for concurrent operation Programmable CAS Latency (CL): 3 and 4 Posted CAS additive latency (AL): 0, 1, 2, 3, and 4 WRITE latency = READ latency - 1 tCK Programmable burst lengths: 4 or 8 Adjustable data-output drive strength 64ms, 8,192-cycle refresh On-die termination (ODT) Designation
64M4 32M8 16M16
MT47H64M4-16 MEG X 4 X 4 MT47H32M8-8 MEG X 8 X 4 MT47H16M16-4 MEG X 16 X 4
For the latest data sheet, please refer to the Micron Web site: http://www.micron.com/datasheets
Options * Configuration 64 Meg x 4 (16 Meg x 4 x 4) 32 Meg x 8 (8 Meg x 8 x 4) 16 Meg x 16 (4 Meg x 16 x 4) * FBGA Package Lead-Free x4x8 60-ball FBGA (8mm x 12mm) x16 84-ball FBGA (8mm x 14)mm * Timing - Cycle Time 5.0ns @ CL = 4 (DDR2-400) 5.0ns @ CL = 3 (DDR2-400) 3.75ns @ CL = 4 (DDR2-533)
ARCHITECTURE
Configuration Refresh Count Row Addressing Bank Addressing
64 MEG X 4
16 Meg x 4 x 4 8K 8K (A0-A12) 4 (BA0 - BA1) 2K (A0-A9, A11)
32 MEG X 8 16 MEG X 16
8 Meg x 8 x 4 8K 8K (A0-A12) 4 (BA0 - BA1) 1K (A0-A9) 4 Meg x 16 x 4 8K 8K (A0-A12) 4 (BA0 - BA1) 512K (A0-A8)
BP BG
Column Addressing
Table 1:
-5 -5E -37E SPEED GRADE -5 -5E -37E
Key Timing Parameters
DATA RATE (MHz) CL = 3 - 400 400 CL = 4 400 400 533
t
RCD (ns) 20 15 15
t RP (ns)
t RC (ns)
20 15 15
65 55 60
09005aef80b12a05 256Mb_DDR2_1.fm - Rev. C 5/04 EN
1
(c)2003 Micron Technology, Inc. All rights reserved.
www..com
256Mb: x4, x8, x16 DDR2 SDRAM
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 FBGA Part Marking Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Mode Register (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 DLL Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Write Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Extended Mode Register (EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 DLL Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Output Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 DQS# Enable/Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 RDQS Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 On Die Termination (ODT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Off-Chip Driver (OCD) Impedance Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Posted CAS Additive Latency (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Extended Mode Register 2 (EMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Extended Mode Register 3 (EMR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Command Truth Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 DESELECT, NOP, and LOAD MODE Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 LOAD MODE (LM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Bank/Row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 ACTIVE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 ACTIVE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 PRECHARGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 SELF REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Precharge Power-Down Clock Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 RESET Function (CKE LOW Anytime) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 ODT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
09005aef80b12a05 DDR2_256MbTOC.fm - Rev. C 5/04 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.
2
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256Mb: x4, x8, x16 DDR2 SDRAM
AC and DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Input Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Input Slew Rate Derating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Power and Ground Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 AC Overshoot/Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Output Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Full Strength Pull-Down Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Full Strength Pull-Up Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 FBGA Package Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 IDD7 Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
09005aef80b12a05 DDR2_256MbTOC.fm - Rev. C 5/04 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.
www..com
256Mb: x4, x8, x16 DDR2 SDRAM
List of Figures
Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: Figure 53: Figure 54: Figure 55: Figure 56: 256Mb DDR2 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 84-ball FBGA Pin Assignment (x16), 8mm x 14mm (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 60-Ball FBGA Pin Assignment (x 4, x 8), 8mm x 12mm (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Functional Block Diagram (64 Meg x 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Functional Block Diagram (32 Meg x 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Functional Block Diagram (16 Meg x 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 DDR2 Power-Up and Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Mode Register (MR) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Extended Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 READ Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Write Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Extended Mode Register 2 (EMR2) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Extended Mode Register 3 (EMR3) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 ACTIVE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Example: Meeting tRRD (MIN) and tRCD (MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 READ Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 READ Interrupted by READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 READ to PRECHARGE BL = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 READ to PRECHARGE BL = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Bank Read - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Bank Read - With Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 x4, x8 Data Output Timing - tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 x16 Data Output Timing - tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Data Output Timing - tAC and tDQSCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 WRITE Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Consecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Nonconsecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 WRITE Interrupted by WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 WRITE to READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 WRITE to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Bank Write-Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Bank Write-with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 WRITE-DM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Self Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Refresh Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 READ to Power-Down Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 READ with Auto Precharge to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 WRITE to Power-Down Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 WRITE with Auto Precharge to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 REFRESH command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 ACTIVE Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PRECHARGE Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 LOAD MODE Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Input Clock Frequency Change During PRECHARGE Power Down Mode . . . . . . . . . . . . . . . . . . . . . .65 RESET Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 ODT Timing for Active or "Fast-Exit" Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 4
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.
09005aef80b12a05 DDR2_256MbLOF.fm - Rev. C 5/04 EN
www..com
256Mb: x4, x8, x16 DDR2 SDRAM
Figure 57: Figure 58: Figure 59: Figure 60: Figure 61: Figure 62: Figure 63: Figure 64: Figure 65: Figure 66: Figure 67: Figure 68: Figure 69: Figure 70: Figure 71: Figure 72: Figure 73: Figure 74: Figure 75: Figure 76: Figure 77: Figure 78: Figure 79: Figure 80: Figure 81: ODT timing for "Slow-Exit" or Precharge Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 ODT "Turn Off" Timings when Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 ODT "Turn-On" Timing when Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 ODT "Turn-Off" Timing when Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 ODT "Turn On" Timing when Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Example Temperature Test Point Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Single-Ended Input Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Differential Input Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Nominal Slew Rate for tIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Tangent Line for tIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Nominal Slew Rate for tIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Tangent Line for tIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 AC Input Test Signal Waveform Command/Address pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 AC Input Test Signal Waveform for Data with DQS,DQS# (differential) . . . . . . . . . . . . . . . . . . . . . . . .82 AC Input Test Signal Waveform for Data with DQS (single-ended) . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 AC Input Test Signal Waveform (differential). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Input Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Differential Output Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Output Slew Rate Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Full Strength Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Full Strength Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Package Drawing 60-Ball (8mmx12mm) FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Package Drawing 84-Ball (8mmx14mm) FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.
www..com
256Mb: x4, x8, x16 DDR2 SDRAM
List of Tables
Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Table 30: Table 31: Table 32: Table 33: Table 34: Table 35: Table 36: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 FBGA Ball Descriptions 64 Meg x 4, 32 Meg x 8, 16 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Truth Table - DDR2 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Truth Table - Current State Bank n - Command to Bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Truth Table - Current State Bank n - Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 READ Using Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 WRITE Using Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 CKE Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 ODT Timing for Active and "Fast-Exit" Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 ODT timing for "Slow-Exit" and Precharge Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 ODT "Turn Off" Timings when Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 ODT "Turn-On" Timing when Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 ODT "Turn-Of" Timing when Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 ODT "Turn On" Timing when Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Absolute Maximum DC Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Recommended DC Operating Conditions (SSTL_18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Input DC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Input AC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Differential Input Logic Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Setup and Hold Time Derating Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Input Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Clock, Data, Strobe, and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Differential AC Output Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Output DC Current Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Output Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Pulldown Current (mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Pull-Up Current (mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 DDR2 IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 General IDD Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 IDD7 Timing Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
09005aef80b12a05 DDR2_256MbLOT.fm - Rev. C 5/04 EN
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256Mb: x4, x8, x16 DDR2 SDRAM
Part Numbers Figure 1: 256Mb DDR2 Part Numbers
Example Part Number: MT47H64M4FT-37E MT47H Configuration Package Speed
Configuration 64 Meg x 4 32 Meg x 8 16 Meg x 16 64M4 32M8 16M16
Package 60-Ball 8 x 12 FBGA Lead-free 84-Ball 8 x 14 FBGA Lead-free BP BG -5 -5E -37E Speed Grade tCK = 5ns, CL = 4 tCK = 5ns, CL = 3 tCK = 3.75ns, CL = 4
NOTE:
Not all speeds and configurations are available.
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Micron's new FBGA Part Marking Decoder makes it easier to understand that part marking. Visit the web site at www.micron.com/ decoder.
General Description
The 256Mb DDR2 SDRAM is a high-speed, CMOS dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quadbank DRAM. The functional block diagrams of the 16 Meg x 16, 32 Meg x 8, and 64 Meg x 4 devices, respectively are shown in the Functional Description section. Ball assignments for the 64 Meg x 4 are shown in Figure 2 and signal descriptions are shown in Table 1. Ball assignments for the 32 Meg x 8 and 64 Meg x 4 are shown in Figure 2 and signal descriptions are shown in Table 2. The 256Mb DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4nprefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR2 SDRAM effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-halfclock-cycle data transfers at the I/O pins.
09005aef80b12a05 256Mb_DDR2_2.fm - Rev. C 5/04 EN
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#). The 256Mb DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR2 SDRAM provides for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read, or a burst write of eight with another write. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAMs, the pipelined, multibank architecture of DDR2 SDRAMs allows for concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a powersaving power-down mode. All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18-compatible. NOTE: 1. The functionality and the timing specifications discussed in this data sheet are for the DLL-enabled mode of operation. 2. Throughout the data sheet, the various figures and text refer to DQs as "DQ." The DQ term is to be interpreted as any and all DQ 7
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256Mb: x4, x8, x16 DDR2 SDRAM
collectively, unless specifically stated otherwise. Additionally, the x16 is divided into two bytes, the lower byte and upper byte. For the lower byte (DQ0 through DQ7) DM refers to LDM and DQS refers to LDQS. For the upper byte (DQ8 through DQ15) DM refers to UDM and DQS refers to UDQS. 3. Complete functionality is described throughout the document and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. 4. Any specific requirement takes precedence over a general statement.
09005aef80b12a05 256Mb_DDR2_2.fm - Rev. C 5/04 EN
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256Mb: x4, x8, x16 DDR2 SDRAM
Figure 2: 84-ball FBGA Pin Assignment (x16), 8mm x 14mm (Top View) Figure 3: 60-Ball FBGA Pin Assignment (x 4, x 8), 8mm x 12mm (Top View)
1 A
VDD
2
NC
3
VSS
4
5
6
7
VSSQ
8
NU/UDQS#
9
VDDQ
B
DQ14 VSSQ UDM UDQS VSSQ DQ15
C
VDDQ DQ9 VDDQ VDDQ DQ8 VDDQ
D
DQ12 VSSQ DQ11 DQ10 VSSQ DQ13
1 A
2
3
4
5
6
7
8
9
VDDQ
E
VDD NC VSS VSSQ
NU/LDQS#
VDDQ
VDD NC,NU/RDQS# VSS
VSSQ
NU/DQS#
F
DQ6 VSSQ LDM LDQS VSSQ DQ7
B
NF,DQ6 VSSQ DM,DM/RDQS DQS VSSQ NF,DQ7
G
VDDQ DQ1 VDDQ VDDQ DQ0 VDDQ
C
VDDQ DQ1 VDDQ VDDQ DQ0 VDDQ
H
DQ4 VSSQ DQ3 DQ2 VSSQ DQ5
D
NF,DQ4 VSSQ DQ3 DQ2 VSSQ NF,DQ5
J
VDDL VREF VSS VSSDL CK VDD
E
VDDL VREF VSS VSSDL CK VDD
K
CKE WE# RAS# CK# ODT
F
CKE WE# RAS# CK# ODT
L
RFU BA0 BA1 CAS# CS#
G
RFU BA0 BA1 CAS# CS# VDD
M
A10 A1 A2 A0
H
A10 A1 A2 A0 VDD
N
VSS A3 A5 A6 A4
J
VSS A3 A5 A6 A4 VSS
P
A7 A9 A11 A8
K
A7 A9 A11 A8 VSS
R
VDD A12 RFU
RFU RFU
L
VDD A12 RFU RFU RFU
09005aef80b12a05 256Mb_DDR2_2.fm - Rev. C 5/04 EN
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256Mb: x4, x8, x16 DDR2 SDRAM
Table 2: FBGA Ball Descriptions 64 Meg x 4, 32 Meg x 8, 16 Meg x 16
TYPE Input DESCRIPTION On-Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ0-DQ15, LDM, UDM, LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ0-DQ7, DQS, DQS#, RDQS, RDQS#, and DM for the x8; DQ0-DQ3, DQS, DQS#, and DM for the x4. The ODT input will be ignored if disabled via the LOAD MODE command. Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/ DQS#) is referenced to the crossings of CK and CK#. Clock Enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for POWER-DOWN entry, POWER-DOWN exit, output disable, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_18 input but will detect a LVCMOS LOW level once Vdd is applied during first powerup. After Vref has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh operation VREF must be maintained. Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple ranks. CS# is considered part of the command code. Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. LDM is DM for lower byte DQ0- DQ7 and UDM is DM for upper byte DQ8-DQ15. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0 and BA1 define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command.
x16 FBGA x4, x8 FBGA BALL BALL ASSIGNMENT ASSIGNMENT SYMBOL K9 F9 ODT
J8, K8
E8, F8
CK, CK#
Input
K2
F2
CKE
Input
L8
G8
CS#
Input
K7, L7, K3
F7, G7, F3
F3, B3
B3
RAS#, CAS#, WE# LDM, UDM
Input
Input
L2, L3
G2, G3
BA0, BA1
Input
09005aef80b12a05 256Mb_DDR2_2.fm - Rev. C 5/04 EN
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256Mb: x4, x8, x16 DDR2 SDRAM
Table 2: FBGA Ball Descriptions 64 Meg x 4, 32 Meg x 8, 16 Meg x 16
TYPE Input DESCRIPTION Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for Read/Write commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Data Input/Output: Bidirectional data bus for 16 Meg x 16.
x16 FBGA x4, x8 FBGA BALL BALL ASSIGNMENT ASSIGNMENT SYMBOL M8, M3, M7, H8, H3, H7, J2, N2, N8, N3, J8, J3, J7, K2, N7, P2, P8, P3, K8, K3, H2, K7, M2, P7, R2 L2 A0-A12
G8, G2, H7, - DQ0- H3, H1, H9, F1, DQ15 F9, C8, C2, D7, D3, D1, D9, B1, B9 - C8, C2, D7, D3, DQ0-DQ7 D1, D9, B1, B9 - C8, C2, D7, D3 DQ0-DQ3 B7, A8 - UDQS, UDQS#
I/O
I/O I/O I/O
Data Input/Output: Bidirectional data bus for 32 Meg x 8.
F7, E8
-
LDQS, LDQS#
-
B7, A8
DQS, DQS#
-
B3, A2
RDQS, RDQS#
A1, E1, J9, M9, A1, E9, H9, L1 R1 J1 E1 A9, C1, C3, C7, A9, C1, C3, C7, C9, E9, G1, G3, C9 G7, G9 J2 E2 A3, E3, J3, N1, A3, E3, J1, K9 P9 J7 E7 A7, B2, B8, D2, A7, B2, B8, D2, D8, E7, F2, F8, D8 H2, H8,
VDD VDDL VDDQ
Data Input/Output: Bidirectional data bus for 64 Meg x 4. Data Strobe for Upper Byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. I/O Data Strobe for Lower Byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center-aligned with write data. LDQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. I/O Data Strobe: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center aligned with write data. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. Output Redundant Data Strobe for 32 Meg x 8 only. RDQS is enabled/ disabled via the LOAD MODE command to the Extended Mode Register (EMR). When RDQS is enabled, RDQS is output with read data only and is ignored during write data. When RDQS is disabled, pin B3 becomes Data Mask (see DM pin). RDQS# is only used when RDQS is enabled AND differential data strobe mode is enabled. Supply Power Supply: 1.8V 0.1V Supply Supply DLL Power Supply: 1.8V 0.1V DQ Power Supply: 1.8V 0.1V. Isolated on the device for improved noise immunity. SSTL_18 reference voltage. Ground. DLL Ground. Isolated on the device from VSS and VSSQ. DQ Ground. Isolated on the device for improved noise immunity.
VREF VSS VSSDL VSSQ
Supply Supply Supply Supply
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256Mb: x4, x8, x16 DDR2 SDRAM
Table 2: FBGA Ball Descriptions 64 Meg x 4, 32 Meg x 8, 16 Meg x 16
TYPE - - - DESCRIPTION No Connect: These pins should be left unconnected. No Function: These pins are used as DQ4-DQ7 on the 32 Meg x 8, but are NF (No Function) on the 16 Meg x 16 configuration. Not Used: If EMR[E10] = 0, A8 and E8 are UDQS# and LDQS#. If EMR[E10] = 1, then A8 and E8 are Not Used. Reserved for Future Use; Bank address bit BA2(L1) for 1Gb, 2Gb, and 4Gb densities. Row address bits A13(R8), A14(R3) and A15(R7) for higher densities.
x16 FBGA x4, x8 FBGA BALL BALL ASSIGNMENT ASSIGNMENT SYMBOL A2, E2 A2, B1, B9, D1, D9 D1, D9, B1, B9 A2, A8 G1, L3, L7, L8 NC NF NU RFU
A8, E8 L1, R3, R7, R8
09005aef80b12a05 256Mb_DDR2_2.fm - Rev. C 5/04 EN
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256Mb: x4, x8, x16 DDR2 SDRAM
Functional Description
The 256Mb DDR2 SDRAM is a high-speed, CMOS dynamic random-access memory containing 268,435,456 bits. The 256Mb DDR2 SDRAM is internally configured as a four-bank DRAM. The 256Mb DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The DDR2 architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR2 SDRAM consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bitwide, one-half-clock-cycle data transfers at the I/O pins. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation.
Figure 4: Functional Block Diagram (64 Meg x 4)
ODT
CKE CK CK# CS# RAS# CAS# WE#
CONTROL LOGIC
COMMAND DECODE
CK, CK#
MODE REGISTERS
REFRESH 13 COUNTER
BANK3 BANK2 BANK1 ROWADDRESS MUX 13 BANK0 ROWADDRESS 8,192 LATCH & DECODER
BANK3 BANK2 BANK1
4
COL0,COL1 DLL 4 MUX DATA DRVRS sw1 R1 DQS GENERATOR 2 DQS, DQS# R1 R2 sw2 R2 DQ0 - DQ3 ODT CONTROL sw1 sw2 VDDQ
15 13
BANK0 MEMORY ARRAY (8,192 x 512 x 16)
16
4 READ LATCH 4 4
SENSE AMPLIFIERS 8,192
INPUT REGISTERS
2 A0-A12, BA0, BA1 ADDRESS REGISTER BANK CONTROL LOGIC
I/O GATING DM MASK LOGIC
1 16 1 4 WRITE FIFO & DRIVERS MASK 1 1 4
1 1 1 1 1 4 4 4 4 4 RCVRS
sw1 R1 R1
sw2 R2 DQS, DQS# R2
15
2
512 (x16)
16 Internal CK, CK#
COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH 9 2
CK OUT 16
4 4 4
sw1 R1 R1
sw2 R2 DM R2
11
CK IN
DATA
COL0,COL1
2 VssQ
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256Mb: x4, x8, x16 DDR2 SDRAM
Figure 5: Functional Block Diagram (32 Meg x 8)
ODT
CKE CK CK# CS# RAS# CAS# WE# CONTROL LOGIC
COMMAND DECODE
CK,CK#
ODT CONTROL sw1 sw2
VDDQ
MODE REGISTERS
REFRESH 13 COUNTER
BANK3 BANK2 BANK1 ROWADDRESS MUX 13 BANK0 ROWADDRESS LATCH & DECODER
BANK3 BANK2 BANK1
8 32 8 READ LATCH 8 8
COL0,COL1 DLL
sw1 8 MUX DATA DRVRS R1 DQS GENERATOR 2 DQS, DQS# sw1 INPUT REGISTERS R1 1 1 1 1 1 8 1 1 8 8 8 8 8 8 8 R1 RCVRS sw1 R1 R1 R1
sw2 R2 DQ0-DQ7 R2
15 13
8,192
BANK0 MEMORY ARRAY (8,192 x 256 x 32)
SENSE AMPLIFIERS 8,192
sw2 R2 DQS, DQS# R2 RDQS#
2 0-A12, 0, BA1 ADDRESS REGISTER BANK CONTROL LOGIC
1
I/O GATING DM MASK LOGIC
32 1 4 WRITE FIFO & DRIVERS MASK
15
2
256 (x32)
32
sw2 R2 R2 RDQS DM
COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH 8
2
internal CK, CK#
CK OUT 32
8
10
CK IN
DATA
COL0,COL1
VssQ
2
Figure 6: Functional Block Diagram (16 Meg x 16)
ODT
CKE CK CK# CS# RAS# CAS# WE# CONTROL LOGIC
COMMAND DECODE
CK,CK#
MODE REGISTERS
REFRESH 13 COUNTER
BANK3 BANK2 BANK1 ROWADDRESS MUX 13 BANK0 ROWADDRESS LATCH & DECODER
BANK3 BANK2 BANK1
16 64 16 READ LATCH 16 16
COL0,COL1 DLL 16 MUX DATA DRVRS sw1 R1 DQS GENERATOR 4 UDQS, UDQS# LDQS, LDQS# R1 R2 sw2 R2 DQ0-DQ15 ODT CONTROL sw1 sw2 VDDQ
15 13
8,192
BANK0 MEMORY ARRAY (8,192 x 128 x 64)
SENSE AMPLIFIERS 8,192
INPUT REGISTERS
2 A0-A12, BA0, BA1 ADDRESS REGISTER
2
2 2 2 2 2 16 16 16 16 16 RCVRS
sw1 R1 R1
sw2 R2 R2 UDQS, UDQS# LDQS, LDQS#
I/O GATING DM MASK LOGIC BANK CONTROL LOGIC
64 2 8 WRITE FIFO & DRIVERS MASK 2 2 16
15
2
128 (x64)
64
COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH 7 2
Internal CK, CK#
CK OUT 64 CK IN DATA
16 16 16
sw1 R1 R1
sw2 R2 UDM, LDM R2
9
COL0,COL1
4 VssQ
09005aef80b12a05 256Mb_DDR2_2.fm - Rev. C 5/04 EN
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Initialization
The following sequence is required for power-up and initialization and is shown in Figure 7. 1. Apply power; if CKE is maintained below 0.2* VDDQ, outputs remain disabled. To guarantee RTT (ODT Resistance) is off, VREF must be valid and a low level must be applied to the ODT pin (all other inputs may be undefined). At least one of the following two sets of conditions (A or B) must be met: A. CONDITION SET A * VDD, VDDL and VDDQ are driven from a single power converter output * VTT is limited to 0.95V MAX * VREF tracks VDDQ/2. B. CONDITION SET B * Apply VDD before or at the same time as VDDL. * Apply VDDL before or at the same time as VDDQ. * Apply VDDQ before or at the same time as VTT and VREF. 2. For a minimum of 200s after stable power and clock (CK, CK#), apply NOP or DESELECT commands and take CKE HIGH. 3. Wait a minimum of 400ns, then issue a PRECHARGE ALL command. 4. Issue an LOAD MODE command to the EMR(2) register. (To issue an EMR(2) command, provide LOW to BA0, provide HIGH to BA1.) 5. Issue a LOAD MODE command to the EMR(3) register. (To issue an EMR(3) command, provide HIGH to BA0 and BA1.) 6. Issue an LOAD MODE command to the EMR register to enable DLL. To issue a DLL ENABLE command, provide LOW to BA1 and A0, provide HIGH to BA0. Bits E7, E8, and E9 must all be set to 0. 7. Issue a LOAD MODE command for DLL Reset. 200 cycles of clock input is required to lock the DLL. (To issue a DLL Reset, provide HIGH to A8 and provide LOW to BA1 and BA0.) CKE must be HIGH the entire time. 8. Issue PRECHARGE ALL command. 9. Issue two or more REFRESH commands. 10. Issue a LOAD MODE command with LOW to A8 to initialize device operation (i.e., to program operating parameters without resetting the DLL). 11. Issue a LOAD MODE command to the EMR to enable OCD default by setting Bits E7, E8, and E9 to 1 and set all other desired parameters. 12. Issue a LOAD MODE command to the EMR to enable OCD exit by setting Bits E7, E8, and E9 to 0 and set all other desired parameters. 13. The DDR2 SDRAM is now intialized and ready for normal operation 200 clocks after DLL Reset in step 7.
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Figure 7: DDR2 Power-Up and Initialization
VDD VDDL
VDDQ VTT1 VREF
tVTD1
T0 CK# CK
tCL
tCK
Ta0
Tb0
Tc0
Td0
Te0
Tf0
Tg0
Th0
Ti0
Tj0
Tk0
Tl0
Tm0
tCL
LVCMOS CKE LOW LEVEL8
SSTL_18 LOW LEVEL8
ODT
COMMAND6
NOP2
PRE
LM9
LM9
LM5
LM
PRE
REF4
REF4
LM10
LM11
LM12
VALID 3
DM7
ADDRESS10
CODE10
CODE10
CODE10
CODE10
CODE10
CODE10
CODE9
CODE9
CODE9
VALID
DQS7 DQ7 Rtt
High-Z
High-Z
High-Z
T = 200s (min)
Power-up: VDD and stable clock (CK, CK#)
T = 400ns (min)
tRP A EMR(2)9
tMRD
tMRD EMR(3)9
tMRD EMR with DLL Enable5
tMRD
t RP
A
tRFC
tRFC
tMRD
tMRD
tMRD
MR w/o DLL Resett 200 cycles of CK3
EMR with OCD Default
EMR with OCD Exit Normal Operation
DON'T CARE
Indicates a break in time scale
MR with DLL Reset
NOTE:
1. VTT is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latch-up. One of the following two conditions (a or b) MUST be met: a) VDD, VDDL, and VDDQ are driven from a single power converter output. VTT may be 0.95V maximum during power up. VREF tracks VDDQ/2. b) Apply VDD before or at the same time as VDDL. Apply VDDL before or at the same time as VDDQ. Apply VDDQ before or at the same time as VTT and VREF. 2. Either a NOP or DESELECT command may be applied. 3. 200 cycles of clock (CK, CK#) are required before a READ command can be issued. CKE must be HIGH the entire time. 4. Two or more REFRESH commands are required. 5. Bits E7, E8, and E9 must all be set to 0 with all other operating parameters of EMRS set as required. 6. PRE = PRECHARGE command, LM = LOAD MODE command, REF = REFRESH command, ACT = ACTIVE command, RA = Row Address, BA = Bank Address. 7. DM represents DM for x4, x8 configuration and UDM, LDM for x16 configuration. DQS represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS# for the appropriate configuration (x4, x8, x16). DQ represents DQ0-DQ3 for x4, DQ0-DQ7 for x8, and DQ0-DQ15 for x16. 8. CKE pin uses LVCMOS input levels prior to state T0. After state T0, CKE pin uses SSTL_18 input levels. 9. The LM command for EMR(2) and EMR(3) may be before or after LM command for MR (Tf0) and EMR (Te0). 10. ADDRESS represents A12-A0 for x4, x8, and A12-A0 for x16, BA0-BA1. A10 should be HIGH at states Tb0 and Tg0 to ensure a PRECHARGE (all banks) command is issued. 11. Bits E7, E8, and E9 must be set to 1 to set OCD default. 12. Bits E7, E8, and E9 must be set to 0 to set OCD exit and all other operating parameters of EMRS set as required.
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Mode Register (MR)
The mode register is used to define the specific mode of operation of the DDR2 SDRAM. This definition includes the selection of a burst length, burst type, CAS latency, operating mode, DLL reset, write recovery, and power-down mode as shown in Figure 8. Contents of the mode register can be altered by reexecuting the LOAD MODE (LM) command. If the user chooses to modify only a subset of the MR variables, all variables (M0-M14) must be programmed when the LOAD MODE command is issued. The mode register is programmed via the LM command (bits BA1-BA0 = 0, 0) and other bits (M12 - M0) will retain the stored information until it is programmed again or the device loses power (except for bit M8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. The LOAD MODE command can only be issued (or reissued) when all banks are in the precharged state. The controller must wait the specified time tMRD before initiating any subsequent operations such as an ACTIVE command. Violating either of these requirements will result in unspecified operation. cant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts.
Figure 8: Mode Register (MR) Definition
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 PD MR WR
9
876543210 DLL TM CAS# Latency BT Burst Length
Mode Register (Mx)
M7 Mode 0 Normal M12 0 1 PD Mode Fast Exit (Normal) Slow Exit (Low Power) 1 Test
M2 M1 M0 Burst Length 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reserved Reserved 4 8 Reserved Reserved Reserved Reserved
M8 DLL Reset 0 1 No Yes
M11 M10 M9 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Write Recovery Reserved 2 3 4 5 6 Reserved Reserved M6 M5 M4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 M3 0 1
Burst Type Sequential Interleaved
Burst Length
Burst length is defined by bits M0-M3 as shown in Figure 8. Read and write accesses to the DDR2 SDRAM are burst-oriented, with the burst length being programmable to either four or eight. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least signifiM14 M13 0 0 1 1 0 1 0 1
CAS Latency Reserved Reserved 2 3 4 5 Reserved Reserved
Mode Register Mode Register (MR) Extended Mode Register (EMR) Extended Mode Register (EMR2) Extended Mode Register (EMR3)
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved. The burst type is selected via bit M3 as shown in Figure 8. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address as shown in Table 3. DDR2 SDRAM supports 4-bit burst and 8-bit burst modes only. For 8-bit burst mode, full interleave address ordering is supported; however, sequential address ordering is nibble-based.
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Table 3: Burst Definition
ORDER OF ACCESSES WITHIN A BURST BURST TYPE = SEQUENTIAL 0,1,2,3 1,2,3,0 2,3,0,1 3,0,1,2 0,1,2,3,4,5,6,7 1,2,3,0,5,6,7,4 2,3,0,1,6,7,4,5 3,0,1,2,7,4,5,6 4,5,6,7,0,1,2,3 5,6,7,4,1,2,3,0 6,7,4,5,2,3,0,1 7,4,5,6,3,0,1,2 BURST TYPE = INTERLEAVED 0,1,2,3 1,0,3,2 2,3,0,1 3,2,1,0 0,1,2,3,4,5,6,7 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 3,2,1,0,7,6,5,4 4,5,6,7,0,1,2,3 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 7,6,5,4,3,2,1,0
STARTING COLUMN ADDRESS BURST (A2, A1, LENGTH A0) 4 000 001 010 011 000 001 010 011 100 101 110 111
8
bits M9-M11) from the last data burst. An example of Write /w AUTO PRECHARGE is shown in Figure 26 on page 30. Write Recovery (WR) values of 2, 3, 4, 5, or 6 clocks may be used for programming bits M9-M11. The user is required to program the value of write recovery, which is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up a noninteger value to the next integer; WR [cycles] = tWR [ns] / tCK [ns]. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Power-Down Mode
Active power-down (PD) mode is defined by bit M12 as shown in Figure 8. PD mode allows the user to determine the active power-down mode, which determines performance vs. power savings. PD mode bit M12 does not apply to precharge power-down mode. When bit M12 = 0, standard Active Power-down mode or `fast-exit' active power-down mode is enabled. The tXARD parameter is used for `fast-exit' active power-down exit timing. The DLL is expected to be enabled and running during this mode. When bit M12 = 1, a lower power active power-down mode or `slow-exit' active power-down mode is enabled. The tXARDS parameter is used for `slow-exit' active power-down exit timing. The DLL can be enabled, but `frozen' during active power-down mode since the exit-to-READ command timing is relaxed. The power difference expected between PD `normal' and PD `low-power' mode is defined in the IDD table.
Operating Mode
The normal operating mode is selected by issuing a LOAD MODE command with bit M7 set to zero, and all other bits set to the desired values as shown in Figure 8. When bit M7 is `1,' no other bits of the mode register are programmed. Programming bit M7 to `1' places the DDR2 SDRAM into a test mode that is only used by the Manufacturer and should NOT be used. No operation or functionality is guaranteed if M7 bit is `1.'
DLL Reset
DLL reset is defined by bit M8 as shown in Figure 8. Programming bit M8 to `1' will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a value of `0' after the DLL RESET function has been issued. Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.
CAS Latency (CL)
The CAS Latency (CL) is defined by bits M4-M6 as shown in Figure 8. CAS Latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The CAS Latency can be set to 3 or 4 clocks. CAS Latency of 2 or 5 clocks are JEDEC optional features and may be enabled in future speed grades. DDR2 SDRAM does not support any half clock latencies. Reserved states should not be used as unknown operation or incompatibility with future versions may result. DDR2 SDRAM also supports a feature called Posted CAS additive latency (AL). This feature allows the READ command to be issued prior to tRCD(MIN) by delaying the internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in more detail in the Extended Mode Register (EMR) and Operational sections.
Write Recovery
Write recovery (WR) time is defined by bits M9-M11 as shown in Figure 8. The WR Register is used by the DDR2 SDRAM during WRITE /w AUTO PRECHARGE operation. During WRITE /w AUTO PRECHARGE operation, the DDR2 SDRAM delays the internal AUTO PRECHARGE operation by WR clocks (programmed in
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Examples of CL = 3 and CL = 4 are shown in Figure 9; both assume AL = 0. If a READ command is registered at clock edge n, and the CAS Latency is m clocks, the data will be available nominally coincident with clock edge n + m (this assumes AL = 0).
Figure 9: CAS Latency (CL)
CK# CK COMMAND DQS, DQS# DQ CL = 3 (AL = 0)
DOUT n DOUT n+1 DOUT n+2 DOUT n+3
T0
T1
T2
T3
T4
T5
T6
READ
NOP
NOP
NOP
NOP
NOP
NOP
CK# CK COMMAND DQS, DQS# DQ
T0
T1
T2
T3
T4
T5
T6
READ
NOP
NOP
NOP
NOP
NOP
NOP
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
CL = 4 (AL = 0)
Burst length = 4 Posted CAS# additive latency (AL) = 0 Shown with nominal tAC, tDQSCK, and tDQSQ
TRANSITIONING DATA
DON'T CARE
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Extended Mode Register (EMR)
The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, ODT (RTT), Posted CAS additive latency (AL), off-chip driver impedance calibration (OCD), DQS# enable/disable, RDQS/RDQS# enable/disable, and OUTPUT disable/enable. These functions are controlled via the bits shown in Figure 10. The extended mode register is programmed via the LOAD MODE (LM) command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the extended mode register will not alter the contents of the memory array, provided it is performed correctly. The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation.
DLL Enable/Disable
The DLL may be enabled or disabled by programming bit E0 during the LOAD MODE command as shown in Figure 10. The DLL must be enabled for normal operation. DLL enable is required during powerup initialization and upon returning to normal operation after having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL should always be followed by resetting the DLL using a LOAD MODE command. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled and reset upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a READ command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.
Figure 10: Extended Mode Register Definition
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
Output Drive Strength
The output drive strength is defined by bit E1 as shown in Figure 10. The normal drive strength for all outputs are specified to be SSTL_18. Programming bit E1 = 0 selects normal (100 percent) drive strength for all outputs. Selecting a reduced drive strength option (bit E1 = 1) will reduce all outputs to approximately 60 percent of the SSTL_18 drive strength. This option is intended for the support of the lighter load and/or point-to-point environments.
14 13 12 11 10 9 8 7 6 5 4 3 2 10 EMR out RDQS DQS# OCD Program RTT Posted CAS# RTT ODS DLL
Extended Mode Register (Ex)
E12 0 1
Outputs Enabled Disabled
E0 E6 E2 RTT (nominal) 0 0 RTT Disabled 01 75 ohm 150 ohm Reserved E1 0 1 10 11 0 1
DLL Enable Enable (Normal) Disable (Test/Debug)
E11 RDQS Enable 0 1 No Yes
Output Drive Strength 100% 60%
DQS# Enable/Disable
The DQS# enable function is defined by bit E10. When enabled (bit E10 = 0), DQS# is the complement of the differential data strobe pair DQS/DQS#. When disabled (bit E10 = 1), DQS is used in a single-ended mode and the DQS# pin is disabled. This function is also used to enable/disable RDQS#. If RDQS is enabled (E11 = 1) and DQS# is enabled (E10 = 0), then both DQS# and RDQS# will be enabled.
E10 DQS# Enable 0 1 Enable Disable
E5 E4 E3 Posted CAS# Additive Latency (AL) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 Reserved Reserved Reserved
E9 E8 E7 OCD Operation 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 OCD Exit Reserved Reserved Reserved OCD Default
RDQS Enable/Disable
The RDQS enable function is defined by bit E11 as shown in Figure 10. This feature is only applicable to the x8 configuration. When enabled (E11 = 1), RDQS is identical in function and timing to data strobe DQS during a READ. During a WRITE operation, RDQS is ignored by the DDR2 SDRAM.
M14 M13 Mode Register 0 0 1 1 0 1 0 1 Mode Register (MR) Extended Mode Register (EMR) Extended Mode Register (EMR2) Extended Mode Register (EMR3)
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Output Enable/Disable
The OUTPUT enable function is defined by bit E12 as shown in Figure 10. When enabled (E12 = 0), all outputs (DQs, DQS, DQS#, RDQS, RDQS#) function normally. When disabled (E12 = 1), all DDR2 SDRAM outputs (DQs, DQS, DQS#, RDQS, RDQS#) are disabled removing output buffer current. The OUTPUT disable feature is intended to be used during IDD characterization of read current. `sw2'. The ODT effective resistance value is selected by enabling switch `sw1,' which enables all `R1' values that are 150 each, enabling an effective resistance of 75 (RTT1(EFF) = `R1' / 2). Similarly, if `sw2' is enabled, all `R2' values that are 300 each, enable an effective ODT resistance of 150 (RTT2(EFF) = `R2'/2). Reserved states should not be used, as unknown operation or incompatibility with future versions may result. The ODT control pin is used to determine when RTT(EFF ) is turned on and off, assuming ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and ODT input pin are only used during active, active power-down (both fast-exit and slow-exit modes), and precharge power-down modes of operation. If SELF REFRESH operation is used, RTT(EFF ) should always be disabled and the ODT input pin is disabled by the DDR2 SDRAM. During power-up and initialization of the DDR2 SDRAM, ODT should be disabled until the EMR command is issued to enable the ODT feature, at which point the ODT pin will determine the RTT(EFF ) value. See "ODT Timing" on page 9 for ODT timing diagrams.
On Die Termination (ODT)
ODT effective resistance RTT(EFF ) is defined by bits E2 and E6 of the EMR as shown in Figure 10. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DDR2 SDRAM controller to independently turn on/off ODT for any or all devices. RTT effective resistance values of 75 and 150 are selectable and apply to each DQ, DQS/DQS#, RDQS/RDQS#, UDQS/UDQS#, LDQS/LDQS#, DM, and UDM/LDM signals. A functional representation of ODT is shown in block diagrams in "Functional Description" on page 13. Bits (E6, E2) determine what ODT resistance is enabled by turning on/off `sw1' or
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Off-Chip Driver (OCD) Impedance Calibration
The OCD function is no longer supported and must be set to the default state. See "Initialization" on page 15 to propertly set OCD defaults. In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued prior to tRCD (MIN) with the requirement that AL tRCD(MIN). A typical application using this feature would set AL = tRCD (MIN) - 1 x tCK. The READ or WRITE command is held for the time of the additive latency (AL) before it is issued internally to the DDR2 SDRAM device. READ Latency (RL) is controlled by the sum of the Posted CAS additive latency (AL) and CAS Latency (CL); RL = AL + CL. Write latency (WL) is equal to READ latency minus one clock; WL = AL + CL - 1 x tCK. An example of a READ latency is shown in Figure 11. An example of a WRITE latency is shown in Figure 12.
T4 T5 T6 T7 T8
Posted CAS Additive Latency (AL)
Posted CAS additive latency (AL) is supported to make the command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. Bits E3-E5 define the value of AL as shown in Figure 10. Bits E3-E5 allow the user to program the DDR2 SDRAM with a CAS# Additive latency of 0, 1, 2, 3, or 4 clocks. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
T0 T1 T2 T3
Figure 11: READ Latency
CK# CK COMMAND DQS, DQS# tRCD (MIN) DQ AL = 2 RL = 5 Burst length = 4 Shown with nominal tAC, tDQSCK, and tDQSQ CAS# latency (CL) = 3 Additive latency (AL) = 2 READ latency (RL) = AL + CL = 5 CL = 3
DOUT n DOUT n+1 DOUT n+2 DOUT n+3
ACTIVE n
READ n
NOP
NOP
NOP
NOP
NOP
NOP
NOP
TRANSITIONING DATA
DON'T CARE
Figure 12: Write Latency
CK# CK COMMAND
ACTIVE n WRITE n
t
T0
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
NOP
NOP
RCD (MIN)
DQS, DQS# AL = 2 DQ WL = AL + CL - 1 = 4 CL - 1 = 2
Din n Din n+1 Din n+2 Din n+3
Burst length = 4
CAS# latency (CL) = 3 Additive latency (AL) = 2 WRITE latency = AL + CL -1 = 4
TRANSITIONING DATA
DON'T CARE
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Extended Mode Register 2 (EMR2)
The Extended Mode Register 2 (EMR2) controls functions beyond those controlled by the mode register. Currently all bits in EMR2 are reserved as shown in Figure 13. The EMR2 is programmed via the LOAD MODE command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the extended mode register will not alter the contents of the memory array, provided it is performed correctly. The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation.
Extended Mode Register 3 (EMR3)
The Extended Mode Register 3 (EMR3) controls functions beyond those controlled by the mode register. Currently all bits in EMR3 are reserved as shown in Figure 14. The EMR3 is programmed via the LOAD MODE command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the extended mode register will not alter the contents of the memory array, provided it is performed correctly. The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation.
Figure 13: Extended Mode Register 2 (EMR2) Definition
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
Figure 14: Extended Mode Register 3 (EMR3) Definition
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 10 EMR(2) 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*
Extended Mode Register (Ex)
14 13 12 11 10 9 8 7 6 5 4 3 2 10 EMR(3) 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*
Extended Mode Register (Ex)
E14 E13 Mode Register 0 0 1 1 0 1 0 1 Mode Register (MR) Extended Mode Register (EMR) Extended Mode Register (EMR2) Extended Mode Register (EMR3)
* E12 (A12)-E0 (A0) are reserved for future use and must all be programmed to '0.'
E14 E13 Mode Register 0 0 1 1 0 1 0 1 Mode Register (MR) Extended Mode Register (EMR) Extended Mode Register (EMR2) Extended Mode Register (EMR3)
* E12 (A12)-E0 (A0) are reserved for future use and must all be programmed to '0.'
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Command Truth Tables
The following tables provide a quick reference of DDR2 SDRAM available commands, including CKE power-down modes, and bank-to-bank commands.
Table 4:
Truth Table - DDR2 Commands
CKE
Notes: 1, 5, and 6 apply to the entire Table. BA1 BA0 BA X X X BA X BA BA BA BA BA X X X X A12 A11
FUNCTION Load Mode Refresh Self Refresh Entry Self Refresh Exit Single Bank Precharge ALL Banks Precharge Bank Activate Write Write with Auto Precharge Read Read with Auto Precharge No Operation Device Deselect Power-Down Entry Power-Down Exit
NOTE:
PREVIOUS CURRENT CYCLE CYCLE H H H L H H H H H H H H H H L H H L H H H H H H H H X X L H
CS# L L L H L L L L L L L L L H H L H L
RAS# CAS# WE# L L L X H L L L H H H H H X X H X H L L L X H H H H L L L L H X X H X H L H H X H L L H L L H H H X X H X H
A10 OP Code X X X L
A9-A0
NOTES 2
X X X X X
X X X X 7 2
H X Row Address Column Column L Address Address Column Column H Address Address Column Column L Address Address Column Column H Address Address X X X X X X X X X X X X
2, 3 2, 3 2, 3 2, 3
4 4
1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock. 2. Bank addresses (BA) BA1-BA0 determine which bank is to be operated upon. BA during a Load Mode command selects which mode register is programmed. 3. Burst reads or writes at BL = 4 cannot be terminated or interrupted. See sections "Read Interrupted by a Read" and "Write Interrupted by a Write" for other restrictions and details. 4. The Power Down Mode does not perform any refresh operations. The duration of power-down is therefore limited by the refresh requirements outlined in the AC parametric section. 5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. See the ODT section for details. 6. "X" means "H or L" (but a defined logic level). 7. Self refresh exit is asynchronous.
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Table 5:
CURRENT STATE Any
Truth Table - Current State Bank n - Command to Bank n
Notes: 1-6; notes appear below and on next page. CS# H L L L L L L L L L L L L L RAS# X H L L L H H L H H L H H L CAS# X H H L L L L H L L H L L H WE# X H H H L H L L H L L H L L COMMAND/ACTION DESELECT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) ACTIVE (select and activate row) REFRESH LOAD MODE READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE (deactivate row in bank or banks) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ( start precharge) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE (start precharge) NOTES
Idle
Row Active
Read (AutoPrecharge Disabled Write (AutoPrecharge Disabled)
NOTE:
7 7 9 9 8 9 9, 11 8 9, 10 9 8, 10
1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH (see Table 5) and after tXSNR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated. 4. The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or allowable commands to the other bank, should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Table 5, and according to Table 6. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the "row active" state. Read with Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write with Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 5. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an REFRESH command and ends when tRFC is met. Once tRFC is met, the DDR2 SDRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a LOAD MODE command and ends when tMRD has been met. Once tMRD is met, the DDR2 SDRAM will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle, and bursts are not in progress. 8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.
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9. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 10. Requires appropriate DM masking. 11. A WRITE command may be applied after the completion of the READ burst.
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Table 6: Truth Table - Current State Bank n - Command to Bank m
CS# H L X L L L L L L L L L L L L L L L L L L L L RAS# X H X L H H L L H H L L H H L L H H L L H H L CAS# X H X H L L H H L L H H L L H H L L H H L L H WE# X H X H H L L H H L L H H L L H H L L H H L L COMMAND/ACTION DESELECT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) Any Command Otherwise Allowed to Bank m ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE NOTES Notes: 1-6; notes appear below and on next page. CURRENT STATE Any Idle Row Activating, Active, or Precharging Read (Auto Precharge Disabled Write (Auto Precharge Disabled.)
7 7
7 7, 9
7, 8 7
Read (with AutoPrecharge)
7, 3a 7, 9, 3a
Write (with AutoPrecharge)
NOTE:
7, 3a 7, 3a
1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSNR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated. Read with Auto Precharge Enabled: See following text - 3a Write with Auto Precharge Enabled: See following text - 3a 3a.The read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. For read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For write with auto precharge, the precharge period begins when tWR ends, with tWR measured as if auto precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. This device supports concurrent auto precharge such that when a read with auto precharge is enabled or a write with auto precharge is enabled any command to other banks is allowed, as long as that command does not interrupt the read or write data transfer already in process. In either case, all other related limitations apply (e.g., contention between read data and write data must be avoided).
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3b.The minimum delay from a read or write command with auto precharge enabled, to a command to a different bank is summarized below. CL = CAS Latency; BL = bust length; WL = WRITE latency FROM COMMAND (BANK n) WRITE with Auto Precharge READ with Auto Precharge 4. 5. 6. 7. TO COMMAND (BANK m) READ or READ w/AP WRITE or WRITE w/AP PRECHARGE or ACTIVE READ or READ w/AP WRITE or WRITE w/AP PRECHARGE or ACTIVE MINIMUM DELAY (WITH CONCURRENT AUTO PRECHARGE) (CL - 1) + (BL / 2) + tWTR (BL / 2) 1 (BL / 2) (BL / 2) + 2 1 UNITS
t t t
CK
CK CK t CK t CK tCK
REFRESH and LOAD MODE commands may only be issued when all banks are idle. Not used. All states and sequences not shown are illegal or reserved. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. Requires appropriate DM masking. 9. A WRITE command may be applied after the completion of the READ burst. 10. tWTR is defined as Min (2 or tWTR/tCK rounded up to the next integer).
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DESELECT, NOP, and LOAD MODE Commands DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in progress are not affected. vents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.
LOAD MODE (LM)
The mode registers are loaded via inputs BA1-BA0 and A12 - A0 for x4 and x8, and A12 - A0 for x16 configurations. BA1-BA0 determine which mode register will be programmed. See "Mode Register (MR)" on page 14. The LOAD MODE command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to perform a NOP (CS# is LOW; RAS#, CAS#, and WE are HIGH). This pre-
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Bank/Row Activation ACTIVE Command
The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA1-BA0 inputs selects the bank, and the address provided on inputs A12 - A0 for x4 and x8, and A12 - A0 for x16 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. The same procedure is used to convert other specification limits from time units to clock cycles. For example, a tRCD(MIN) specification of 20ns with a 266 MHz clock (tCK = 3.75ns) results in 5.3 clocks rounded up to 6. This is reflected in Figure 17, which covers any case where 5 < tRCD (MIN) / tCK 6. Figure 17 also shows the case for tRRD where 2 < tRRD (MIN) / tCK 3. A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by t RRD.
ACTIVE Operation
Before any READ or WRITE commands can be issued to a bank within the DDR2 SDRAM, a row in that bank must be "opened" (activated). This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated, as shown in Figure 15.
Figure 15: ACTIVE Command
CK# CK CKE CS# RAS# CAS# WE# ADDRESS BANK ADDRESS
Row
Bank
DON'T CARE
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READs READ Command
The READ command is used to initiate a burst read access to an active row. The value on the BA1-BA0 inputs selects the bank, and the address provided on inputs A0-i (where i = A9 for x16, A9 for x8, or A9, A11 for x4) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. negative clock edge (i.e., at the next crossing of CK and CK#). Figure 18 shows examples of READ latency based on different AL and CL settings.
Figure 16: READ Command
CK# CK CKE CS# RAS# CAS# WE# ADDRESS AUTO PRECHARGE
Col ENABLE A10 DISABLE
READ Operation
READ bursts are initiated with a READ command, as shown in Figure 16. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is automatically precharged at the completion of the burst. If auto precharge is disabled, the row will be left open after the completion of the burst. During READ bursts, the valid data-out element from the starting column address will be available READ latency (RL) clocks later. READ latency (RL) is defined as the sum of Posted CAS additive latency (AL) and CAS Latency (CL); RL = AL + CL. The value for AL and CL are programmable via the MR and EMR commands, respectively. Each subsequent data-out element will be valid nominally at the next positive or
BANK ADDRESS
Bank
DON'T CARE
Figure 17: Example: Meeting tRRD (MIN) and tRCD (MIN)
CK# CK COMMAND
ACT NOP NOP ACT NOP NOP NOP NOP NOP RD/WR
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
ADDRESS BA0, BA1
Row
Row
Col
Bank x
tRRD
Bank y
tRCD
Bank y
DON'T CARE
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Figure 18: READ Latency
T0 CK# CK COMMAND ADDRESS
READ Bank a, Col n NOP NOP NOP NOP NOP
T1
T2
T3
T3n
T4
T4n
T5
RL = 3 (AL = 0, CL = 3) DQS, DQS# DQ
DO n
T0 CK# CK COMMAND ADDRESS
READ Bank a, Col n
T1
T2
T3
T4
T4n
T5
T5n
NOP
NOP
NOP
NOP
NOP
AL = 1 RL = 4 (AL + CL) DQS,DQS# DQ T0 CK# CK COMMAND ADDRESS
READ Bank a, Col n NOP NOP
CL = 3
DO n
T1
T2
T3
T3n
T4
T4n
T5
NOP
NOP
NOP
RL = 4 (AL = 0, CL = 4) DQS, DQS# DQ
DO n
DON'T CARE
TRANSITIONING DATA
NOTE:
1. 2. 3. 4.
DO n = data-out from column n. Burst length = 4. Three subsequent elements of data-out appear in the programmed order following DO n. Shown with nominal tAC, tDQSCK, and tDQSQ.
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DQS/DQS# is driven by the DDR2 SDRAM along with output data. The initial LOW state on DQS and HIGH state on DQS# is known as the READ preamble (tRPRE). The LOW state on DQS and HIGH state on DQS# coincident with the last data-out element is known as the read postamble (tRPST). Upon completion of a burst, assuming no other commands have been initiated, the DQs will go HighZ. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out window hold), the valid data window are depicted in Figure 27 on page 40 and Figure 28 on page 41. A detailed explanation of tDQSCK (DQS transition skew to CK) and tAC (data-out transition skew to CK) is shown in Figure 29 on page 42. Data from any READ burst may be concatenated with data from a subsequent READ command to provide a continuous flow of data. The first data element from the new burst follows the last element of a completed burst. The new READ command should be issued x cycles after the first READ command, where x equals BL / 2 cycles. This is shown in Figure 19.
Figure 19: Consecutive READ Bursts
T0 CK# CK COMMAND ADDRESS
READ Bank, Col n
t
T1
T2
T3
T3n
T4
T4n
T5
T5n
T6
T6n
NOP
READ Bank, Col b
NOP
NOP
NOP
NOP
CCD
RL = 3 DQS, DQS# DQ
DO n DO b
T0 CK# CK COMMAND ADDRESS
READ Bank, Col n
t
T1
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
T6n
NOP
READ Bank, Col b
NOP
NOP
NOP
NOP
CCD RL = 4
DQS, DQS# DQ DON'T CARE
NOTE:
DO n DO b
TRANSITIONING DATA
1. 2. 3. 4. 5. 6.
1. DO n (or b) = data-out from column n (or column b). Burst length = 4. Three subsequent elements of data-out appear in the programmed order following DO n. Three subsequent elements of data-out appear in the programmed order following DO b. Shown with nominal tAC, tDQSCK, and tDQSQ. Example applies only when READ commands are issued to same device.
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Figure 20: Nonconsecutive READ Bursts
T0 CK# CK COMMAND ADDRESS
READ Bank, Col n NOP NOP READ Bank, Col b NOP NOP NOP NOP NOP
T1
T2
T3
T3n
T4
T4n
T5
T6
T6n
T7
T7n
T8
CL = 3 DQS, DQS# DQ T0 CK# CK COMMAND ADDRESS
READ Bank, Col n NOP NOP READ Bank, Col b NOP NOP NOP NOP NOP DO n DO b
T1
T2
T3
T4
T4n
T5
T5n
T6
T7
T7n
T8
CL = 4 DQS, DQS#
NOTE:
1. 2. 3. 4. 5. 6.
DO n (or b) = data-out from column n (or column b). Burst length = 4. Three subsequent elements of data-out appear in the programmed order following DO n. Three subsequent elements of data-out appear in the programmed order following DO b. Shown with nominal tAC, tDQSCK, and tDQSQ. Example applies when READ commands are issued to different devices or nonconsecutive READs.
Nonconsecutive read data is illustrated in Figure 20 on page 34. Full-speed random read accesses within a page (or pages) can be performed. DDR2 SDRAM supports the use of concurrent auto precharge timing, which is shown in Table 7 on page 36. DDR2 SDRAM does not allow interrupting or truncating of any READ burst using BL = 4 operations. Once the BL = 4 READ command is registered, it must be allowed to complete the entire READ burst. How-
ever, a READ (with AUTO PRECHARGE disabled) using BL = 8 operation may be interrupted and truncated ONLY by another READ burst as long as the interruption occurs on a four-bit boundary due to the 4n prefetch architecture of DDR2 SDRAM. READ burst BL = 8 operations may not be interrupted or truncated with any command except another READ command as shown in Figure 21 on page 35.
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Figure 21: READ Interrupted by READ
CK# CK COMMAND ADDRESS A10 DQS, DQS# DQ CL = 3 (AL = 0)
tCCD DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
READ1
NOP5
READ3
NOP5
VALID
VALID
VALID
VALID
VALID
VALID
VALID2
VALID2 VALID4
CL = 3 (AL = 0) TRANSITIONING DATA DON'T CARE
NOTE:
1. Burst length = 8 required, AUTO PRECHARGE must be disabled (A10 = LOW). 2. READ command can be issued to any valid bank and row address (READ command at T0 and T2 can be either same bank or different bank). 3. Interupting READ command must be issued exactly 2 x tCK from previous READ. 4. AUTO PRECHARGE can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the interupting READ command. 5. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command cannot be issued to banks used for READs at T0 and T2. 6. Example shown uses additive latency = 0; CAS Latency = 3, BL = 8, shown with nominal tAC, tDQSCK, and tDQSQ.
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Table 7:
FROM COMMAND (BANK n) READ with Auto Precharge
READ Using Concurrent Auto Precharge
BL = burst length. TO COMMAND (BANK m) READ or READ w/AP WRITE or WRITE w/AP PRECHARGE or ACTIVE MINIMUM DELAY (WITH CONCURRENT AUTO PRECHARGE) (BL/2) (BL/2) + 2 1
UNITS
t
CK CK
tCK t
Data from any READ burst must be completed before a subsequent WRITE burst is allowed. An example of a READ burst followed by a WRITE burst is shown in Figure 24. The tDQSS (MIN) case is shown; the tDQSS (MAX) case has a longer bus idle time. (tDQSS [MIN] and tDQSS [MAX] are defined in the section on WRITEs.) A READ burst may be followed by a PRECHARGE command to the same bank provided that AUTO PRECHARGE is not activated. Examples of READ to PRECHARGE are shown in Figure 22 for BL=4 and Figure 23 for BL=8. The delay from READ command to PRECHARGE command to the same bank is AL + BL/2 + tRTP - 2 clocks. If A10 is HIGH when a READ command is issued, the READ with AUTO PRECHARGE function is engaged. The DDR2 SDRAM starts an AUTO PRECHARGE operation on the rising edge which is (AL +
BL/2) cycles later than the READ with AP command if tRAS (MIN) and tRTP are satisfied. If tRAS (MIN) is not satisfied at the edge, the start point of AUTO PRECHARGE operation will be delayed until tRAS (MIN) is satisfied. If tRTP (MIN) is not satisfied at the edge, the start point of the AUTO PRECHARGE operation will be delayed until tRTP (MIN) is satisfied. In case the internal precharge is pushed out by tRTP tRP starts at the , point where the internal precharge happens (not at the next rising clock edge after this event). So for BL = 4 the minimum time from READ with AP to the next activate command becomes AL + (tRTP + tRP)* (see Figure 22 on page 36); for BL = 8 the time from READ with AP to the next activate is AL + 2 clocks + (tRTP + tRP)* (see Figure 23 on page 37), where * means each parameter term is divided by tCK and rounded up to the next integer. In any event, internal precharge does not start earlier than two clocks after the last four-bit prefetch.
Figure 22: READ to PRECHARGE BL = 4
4-bit prefetch CK# CK COMMAND
READ NOP NOP PRECHARGE NOP NOP ACTIVE NOP
T0
T1
T2
T3
T4
T5
T6
T7
AL + BL/2 + tRTP - 2 clocks ADDRESS A10 AL=1 DQS, DQS# tRTP(MIN) DQ tRAS(MIN) tRC(MIN)
DOUT DOUT DOUT DOUT
Bank a
Bank a
Bank a
Valid
Valid
CL = 3
tRP(MIN)
Read Latency = 4 (AL = 1, CL = 3), BL = 4, tRTP 2 clocks Shown with nominal tAC, tDQSCK, and tDQSQ
TRANSITIONING DATA
DON'T CARE
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Figure 23: READ to PRECHARGE BL = 8
first 4-bit prefetch CK# CK COMMAND
READ NOP NOP NOP NOP PRECHARGE NOP NOP ACTIVE
second 4-bit prefetch T2 T3 T4 T5 T6 T7 T8
T0
T1
AL + BL/2 + tRTP - 2 clocks ADDRESS A10 AL=1 DQS, DQS# DQ
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
Bank a
Bank a
Bank a
Valid
Valid
CL = 3
tRTP(MIN) tRAS(MIN) tRC(MIN) Read Latency = 4 (AL=1, CL=3), BL=8, tRTP 2 clocks Shown with nominal tAC, tDQSCK, and tDQSQ
tRP(MIN)
TRANSITIONING DATA
DON'T CARE
Figure 24: READ to WRITE
CK# CK COMMAND DQS, DQS#
t
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
ACTIVE n
READ n
NOP
NOP
NOP
WRITE n
NOP
NOP
NOP
NOP
NOP
NOP
RCD = 3
DOUT n
WL = RL - 1 = 4
DOUT n+1 DOUT n+2 DOUT n+3 Din n Din n+1 Din n+2 Din n+3
DQ AL = 2 RL = 5 Burst length = 4 Shown with nominal tAC, tDQSCK, and tDQSQ CAS# read latency (CL) = 3 Posted CAS# additive latency (AL) = 2 CL = 3
TRANSITIONING DATA
DON'T CARE
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Figure 25: Bank Read - Without Auto Precharge
CK# CK
tCK tCH tCL
T0
T1
T2
T3
T4
T5
T6
T7
T7n
T8
T8n
CKE
COMMAND5
NOP6
ACT
NOP6
NOP6
READ2
NOP6
PRE7
NOP6
NOP6
ACT
tRTP 8 ADDRESS
RA Col n RA
ALL BANKS
A10
RA
3
ONE BANK
RA
BA0, BA1
Bank x tRCD tRAS7 tRC
Bank x
Bank x4
Bank x
CL = 3
tRP
DM
Case 1: tAC (MIN) and tDQSCK (MIN) DQS, DQS#
tLZ (MIN)
tRPRE
tDQSCK (MIN)
tRPST
DQ1
tLZ (MIN)
DO n tAC (MIN) tHZ (MIN)
Case 2: tAC (MAX) and tDQSCK (MAX) DQS, DQS#
tLZ (MAX)
tRPRE
tDQSCK (MAX)
tRPST
DQ1
tLZ (MIN)
DO n tAC (MAX) tHZ (MAX)
TRANSITIONING DATA DON'T CARE
NOTE:
1. 2. 3. 4. 5. 6. 7. 8.
DO n = data-out from column n; subsequent elements are applied in the programmed order. Burst length = 4 and AL = 0 in the case shown. Disable auto precharge. "Don't Care" if A10 is HIGH at T5. PRE = PRECHARGE, ACT = ACTIVE, RA = row address, BA = bank address. NOP commands are shown for ease of illustration; other commands may be valid at these times. The PRECHARGE command can only be applied at T6 if tRAS minimum is met. Read to Precharge = AL +BL/2 + tRTP-2 clocks.
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Figure 26: Bank Read - With Auto Precharge
CK# CK
tCK tCH tCL
T0
T1
T2
T3
T4
T5
T6
T7
T7n
T8
T8n
CKE
COMMAND5
NOP5
ACT
NOP5
READ2,6
NOP5
NOP5
NOP5
NOP5
NOP5
ACT
ADDRESS
RA
Col n
RA
3
A10
RA
RA
BA0, BA1
Bank x tRCD tRAS tRC
Bank x
Bank x
AL=1 tRTP
CL = 3
tRP
DM
Case 1: tAC (MIN) and tDQSCK (MIN) DQS,DQS#
tLZ (MIN)
tRPRE
tDQSCK (MIN)
tRPST
DQ1
tLZ (MIN)
DO n tAC (MIN) tHZ (MIN)
Case 2: tAC (MAX) and tDQSCK (MAX) DQS, DQS#
tLZ (MAX)
tRPRE
tDQSCK (MAX)
tRPST
DQ1 4-bit prefetch
t Internal LZ (MAX) precharge
DO n tAC (MAX) tHZ (MAX)
TRANSITIONING DATA DON'T CARE
NOTE:
1. 2. 3. 4. 5. 6.
DO n = data-out from column n; subsequent elements are applied in the programmed order. Burst length = 4, RL = 4 (AL = 1, CL = 3) in the case shown. Enable auto precharge. ACT = ACTIVE, RA = row address, BA = bank address. NOP commands are shown for ease of illustration; other commands may be valid at these times. The DDR2 SDRAM internally delays auto precharge until both tRAS (MIN) and tRTP (MIN) have been satisfied.
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Figure 27: x4, x8 Data Output Timing - tDQSQ, tQH, and Data Valid Window
T1 T2 T2n T3 T3n T4
CK# CK
tHP5 tHP5 tDQSQ3 tHP5 tDQSQ3 tHP5 tHP5 tDQSQ3 tHP5 tDQSQ3
DQS# DQS1
DQ (Last data valid) DQ2 DQ2 DQ2 DQ2 DQ2 DQ2 DQ (First data no longer valid)
tQH4 tQH4 tQH4 tQH4
DQ (Last data valid) DQ (First data no longer valid)
T2 T2
T2n T2n
T3 T3
T3n T3n
All DQs and DQS, collectively6 Earliest signal transition Latest signal transition
T2
T2n
T3
T3n
Data Valid window
Data Valid window
Data Valid window
Data Valid window
NOTE:
1. DQs transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at T2n are "early DQS," at T3 are "nominal DQS," and at T3n are "late DQS." 2. For a x4, only two DQs apply. 3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transitions and ends with the last valid transition of DQs . 4. tQH is derived from tHP: tQH = tHP - tQHS. 5. tHP is the lesser of tCL or tCH clock transitions collectively when a bank is active. 6. The data valid window is derived for each DQS transition and is defined as tQH minus tDQSQ.
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Figure 28: x16 Data Output Timing - tDQSQ, tQH, and Data Valid Window
CK# CK
T1 T2 T2n T3 T3n T4 tHP5 tHP5 tDQSQ3 tHP5 tHP5 tDQSQ3 tHP5 tDQSQ3 tHP5 tDQSQ3
LDSQ# LDQS1 DQ (Last data valid)2 DQ2 DQ2 DQ2 DQ2 DQ2 DQ2 DQ (First data no longer valid)2
tQH4 tQH4 tQH4 tQH4
Lower Byte
DQ (Last data valid)2 DQ (First data no longer valid)2 DQ0-DQ7 and LDQS, collectively6
T2 T2 T2
T2n T2n T2n
T3 T3 T3
T3n T3n T3n
Data Valid window
tDQSQ3
Data Valid window
tDQSQ3
Data Valid window
tDQSQ3
Data Valid window
tDQSQ3
UDQS# UDQS1 DQ (Last data valid)7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ (First data no longer valid)7
tQH4 tQH4 tQH4 tQH4
Upper Byte
DQ (Last data DQ (First data no longer
valid)7 valid)7
T2 T2 T2 Data Valid window
T2n T2n T2n Data Valid window
T3 T3 T3
T3n T3n T3n
DQ8-DQ15 and UDQS, collectively6
Data Valid Data Valid window window
NOTE:
1. DQs transitioning after DQS transitions define the tDQSQ window. LDQS defines the lower byte, and UDQS defines the upper byte. 2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7. 3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transitions and ends with the last valid transition of DQs. 4. tQH is derived from tHP: tQH = tHP - tQHS. 5. tHP is the lesser of tCL or tCH clock transitions collectively when a bank is active. 6. The data valid window is derived for each DQS transition and is tQH minus tDQSQ. 7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
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Figure 29: Data Output Timing - tAC and tDQSCK
T07 CK# CK tLZ (MIN) tRPRE tDQSCK1 (MAX) tDQSCK1 (MIN) tHZ (MAX) tDQSCK1 (MAX) tDQSCK1 (MIN) tRPST T1 T2 T3 T3n T4 T4n T5 T5n T6 T6n T7
DQS#/DQS, or LDQS#/LDQS / UDQ#/UDQS2 DQ (Last data valid) DQ (First data valid) All DQs collectively3
T3 T3 T3 tLZ (MIN)
T3n T3n T3n
T4 T4 T4
T4n T4n T4n
T5 T5 T5
T5n T5n T5n
T6 T6 T6
T6n T6n T6n
tAC4 (MIN)
tAC4 (MAX)
tHZ (MAX)
NOTE:
1. 2. 3. 4. 5. 6. 7.
is the DQS output window relative to CK and is the"long-term" component of DQS skew. DQs transitioning after DQS transitions define tDQSQ window. All DQs must transition by tDQSQ after DQS transitions, regardless of tAC. tAC is the DQ output window relative to CK and is the"long term" component of DQ skew. tLZ (MIN) and tAC (MIN) are the first valid signal transitions. tHZ (MAX) and tAC (MAX) are the latest valid signal transitions. READ command with CL=3, AL=0 issued at T0.
tDQSCK
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WRITEs WRITE Command
The WRITE command is used to initiate a burst write access to an active row. The value on the BA1BA0 inputs selects the bank, and the address provided on inputs A0-i (where i = A9 for x8 and x16; or A9, A11 for x4) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses.
WRITE Operation
WRITE bursts are initiated with a WRITE command, as shown in Figure 30. DDR2 SDRAM uses Write Latency (WL) equal to Read Latency minus 1 clock cycle (WL = RL - 1 = AL + CL - 1). The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and subsequent data elements will be registered on successive edges of DQS. The LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in element is known as the write postamble. The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from 75 percent to 125 percent of one clock cycle). All of the WRITE diagrams show the nominal case, and where the two extreme cases (i.e., tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have also been included. Figure 31 shows the nominal case and the extremes of t DQSS for a burst of 4. Upon completion of a burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored. Data for any WRITE burst may be concatenated with a subsequent WRITE command to provide continuous flow of input data. The first data element from the new burst is applied after the last element of a completed burst. The new WRITE command should be issued x cycles after the first WRITE command, where x equals BL/2. Figure 32 shows concatenated bursts of 4. An example of nonconsecutive WRITEs is shown in Figure 33. Full-speed random write accesses within a page or pages can be performed as shown in Figure 34. DDR2 SDRAM supports concurrent auto precharge options shown in Table 8. DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4 operation. Once the BL = 4 WRITE command is registered, it must be allowed to complete the entire WRITE burst cycle. However, a WRITE (with AUTO PRECHARGE disabled) using BL = 8 operations may be interrupted and trun-
Figure 30: WRITE Command
CK# CK CKE CS# RAS# CAS# HIGH
WE#
ADDRESS
CA
EN AP
A10
DIS AP
BANK ADDRESS
BA
CA = column address BA = bank address EN AP = enable auto precharge DIS AP = disable auto precharge DON'T CARE
Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location (Figure 40).
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cated ONLY by another WRITE burst as long as the interruption occurs on a four-bit boundary due to the 4n prefetch architecture of DDR2 SDRAM. WRITE burst BL = 8 operations may NOT be interrupted or truncated with any command except another WRITE command as shown in Figure 35. Data for any WRITE burst may be followed by a subsequent READ command. To follow a WRITE tWTR should be met as shown in Figure 36. tWTR is defined as Min(2 or tWTR/tCK rounded up to the next integer). Data for any WRITE burst may be followed by a subsequent PRECHARGE command. tWR must be met as shown in Figure 30. tWR starts at the end of the data burst regardless of the data mask condition.
Table 8:
FROM COMMAND (BANK n) WRITE with Auto Precharge
WRITE Using Concurrent Auto Precharge
CL = CAS latency, BL = burst length TO COMMAND (BANK m) READ or READ w/AP WRITE or WRITE w/AP PRECHARGE or ACTIVE MINIMUM DELAY (WITH CONCURRENT AUTO PRECHARGE) (CL-1) + (BL/2) + (BL/2) 1
tWTR
UNITS
tCK tCK tCK
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Figure 31: WRITE Burst
T0 CK# CK COMMAND ADDRESS
tDQSS (NOM) WRITE Bank a, Col b NOP NOP NOP NOP
T1
T2
T2n
T3
T3n
T4
tDQSS
DQS, DQS# DQ DM
tDQSS (MIN) DI b
tDQSS
DQS, DQS# DQ DM
tDQSS (MAX) DI b
tDQSS
DQS, DQS# DQ DM
DI b
DON'T CARE
TRANSITIONING DATA
NOTE:
1. 2. 3. 4.
DI b = data-in for column b. Three subsequent elements of data-in are applied in the programmed order following DI b. A burst of 4 is shown with AL = 0, CL = 3; thus, WL = 2. A10 is LOW with the WRITE command (auto precharge is disabled).
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Figure 32: Consecutive WRITE to WRITE
T0 CK# CK COMMAND T1 T1n T2 T2n T3 T3n T4 T4n T5 T5n T6
WRITE
NOP
tCCD
WRITE
NOP
NOP
NOP
NOP
WL = 2 ADDRESS
tDQSS (NOM) Bank, Col b tDQSS Bank, Col n
WL = 2
DQS, DQS# DQ DM DON'T CARE TRANSITIONING DATA
DI b DI n
NOTE:
1. 2. 3. 4. 5.
DI b, etc. = data-in for column b, etc. Three subsequent elements of data-in are applied in the programmed order following DI b. Three subsequent elements of data-in are applied in the programmed order following DI n. A burst of 4 is shown with AL = 0, CL = 3; thus, WL = 2. Each WRITE command may be to any bank.
Figure 33: Nonconsecutive WRITE to WRITE
T0 CK# CK COMMAND T1 T2 T2n T3 T3n T4 T4n T5 T5n T6 T6n
WRITE
NOP
NOP
WRITE
NOP
NOP
NOP
WL = 2 ADDRESS
tDQSS (NOM) Bank, Col b tDQSS Bank, Col n
WL = 2
DQS, DQS# DQ DM
DI b DI n
DON'T CARE
TRANSITIONING DATA
NOTE:
1. 2. 3. 4. 5.
DI b, etc. = data-in for column b, etc. Three subsequent elements of data-in are applied in the programmed order following DI b. Three subsequent elements of data-in are applied in the programmed order following DI n. A burst of 4 is shown. AL = 0, CL = 3; thus, WL = 2. Each WRITE command may be to any bank.
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Figure 34: Random WRITE Cycles
T0 CK# CK COMMAND T1 T1n T2 T2n T3 T3n T4 T4n T5 T5n T6
WRITE
NOP
tCCD
WRITE
NOP
NOP
NOP
NOP
WL = 2 ADDRESS
tDQSS (NOM) Bank, Col b tDQSS Bank, Col n
WL = 2
DQS, DQS# DQ DM DON'T CARE TRANSITIONING DATA
DI b DI n
NOTE:
1. 2. 3. 4. 5.
DI b, etc. = data-in for column b, etc. Three subsequent elements of data-in are applied in the programmed order following DI b. Three subsequent elements of data-in are applied in the programmed order following DI n. An burst of 4 is shown. AL = 0, CL = 3; thus, WL = 2. Each WRITE command may be to any bank.
Figure 35: WRITE Interrupted by WRITE
CK# CK COMMAND ADDRESS A10 DQS, DQS# DQ WL = 3 2 clock requirement
DIN a DIN a+1 DIN a+2 DIN a+3 DIN b DIN b+1 DIN b+2 DIN b+3 DIN b+4 DIN b+5 DIN b+6 DIN b+7
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
WRITE1 a VALID2
NOP5
WRITE3 b VALID2
NOP5
NOP5
NOP5
NOP5
VALID6
VALID6
VALID6
VALID4
WL = 3
TRANSITIONING DATA
DON'T CARE
NOTE:
1. Burst length = 8 required, AUTO PRECHARGE must be disabled (A10 = LOW). 2. WRITE command can be issued to any valid bank and row address (WRITE command at T0 and T2 can be either same bank or different bank). 3. Interupting WRITE command must be issued exactly 2 x tCK from previous WRITE. 4. AUTO PRECHARGE can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the interupting WRITE command. 5. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command can not be issued to banks used for WRITEs at T0 and T2. 6. Earliest WRITE-to-PRECHARGE timing for WRITE at T0 is WL + BL/2 + tWR where tWR starts with T7 and not T5 (since BL = 8 from MR and not the truncated length). 7. Example shown uses Additive Latency = 0; CAS Latency = 4, BL = 8.
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Figure 36: WRITE to READ
T0 CK# CK COMMAND
WRITE NOP NOP NOP NOP NOP tWTR7 READ NOP NOP NOP
T1
T2
T2n
T3
T3n
T4
T5
T6
T7
T8
T9
T9n
ADDRESS
tDQSS (NOM)
Bank a, Col b tDQSS
Bank a, Col n
CL = 3
DQS, DQS# DQ DM
tDQSS (MIN) tDQSS DI b Dout
CL = 3
DQS, DQS# DQ DM
tDQSS (MAX) tDQSS DI b Dout
CL = 3
DQS, DQS# DQ DM DON'T CARE TRANSITIONING DATA
DI b Dout
NOTE:
1. 2. 3. 4. 5. 6. 7.
DI b = data-in for column b; Dout n = data out from column n. A burst of 4 is shown; AL = 0, CL = 3; thus, WL = 2. One subsequent element of data-in is applied in the programmed order following DI b. tWTR is referenced from the first positive CK edge after the last data-in pair. A10 is LOW with the WRITE command (auto precharge is disabled). tWTR is defined as Min(2 or tWTR/tCK rounded up to the next integer). Required for any READ following a WRITE to the same device.
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Figure 37: WRITE to PRECHARGE
T0 CK# CK COMMAND
WRITE NOP NOP NOP NOP NOP tWR NOP PRE7 tRP Bank, (a or all) tDQSS
T1
T2
T2n
T3
T3n
T4
T5
T6
T7
ADDRESS
tDQSS (NOM)
Bank a, Col b
DQS# DQS DQ DM
tDQSS (MIN) tDQSS DI b
DQS# DQS DQ DM
tDQSS (MAX) tDQSS DI b
DQS# DQS DQ DM DON'T CARE TRANSITIONING DATA
DI b
NOTE:
1. 2. 3. 4. 5.
DI b = data-in for column b. Three subsequent elements of data-in are applied in the programmed order following DI b. BL=4; CL = 3; AL = 0; thus, WL = 2. t WR is referenced from the first positive CK edge after the last data-in pair. The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE and WRITE commands may be to different banks, in which case tWR is not required and the PRECHARGE command could be applied earlier. 6. A10 is LOW with the WRITE command (auto precharge is disabled). 7. PRE = PRECHARGE command.
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Figure 38: Bank Write-Without Auto Precharge
CK# CK T0 T1 T2 T3 T4 T5 T5n T6 T6n T7 T8 T9
tCK
tCH
tCL
CKE
COMMAND5
NOP6
ACT
NOP6
WRITE2
NOP6
NOP6
NOP6
NOP6
NOP6
PRE
ADDRESS
RA
Col n
ALL BANKS
A10
RA
3
ONE BANK
BA0, BA1
Bank x tRCD tRAS
Bank x
Bank x4
WL=2
tWR
notes appear below and on next page.
tDQSS (NOM)
tRP
DQS, DQS#
tWPRE tDQSL tDQSH tWPST
DQ1 DM
DI n
DON'T CARE
TRANSITIONING DATA
NOTE:
1. 2. 3. 4. 5. 6. 7. 8.
DI n = data-in from column n; subsequent elements are applied in the programmed order. BL = 4, AL = 0, and WL = 2 in the case shown. Disable auto precharge. "Don't Care" if A10 is HIGH at T8. PRE = PRECHARGE, ACT = ACTIVE, RA = row address, BA = bank address. NOP commands are shown for ease of illustration; other commands may be valid at these times. t DSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6. tDSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7.
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Figure 39: Bank Write-with Auto Precharge
CK# CK T0 T1 T2 T3 T4 T5 T5n T6 T6n T7 T8 T9
tCK
tCH
tCL
CKE
COMMAND4
NOP5
ACT
NOP5
WRITE2
NOP5
NOP5
NOP5
NOP5
NOP5
NOP5
ADDRESS
RA
Col n 3
A10
RA
BA0, BA1
Bank x tRCD tRAS
Bank x
WL = 2
WR8
tRP
tDQSS (NOM)
DQS,DQS#
tWPRE tDQSL tDQSH tWPST
DQ1 DM
DI n
TRANSITIONING DATA
DON'T CARE
NOTE:
1. 2. 3. 4. 5. 6. 7. 8.
DI n = data-in from column n; subsequent elements are applied in the programmed order. Burst length = 4, AL = 0, and WL = 2 shown. Enable auto precharge. ACT = ACTIVE, RA = row address, BA = bank address. NOP commands are shown for ease of illustration; other commands may be valid at these times. tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6. tDSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7. WR is programmed via MR[11,10,9] and is calculated by dividing tWR(ns) by tCK and rounding up to the next integer value.
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Figure 40: WRITE-DM Operation
CK# CK T0 T1 T2 T3 T4 T5 T6 T6n T7 T7n T8 T9 T10 T11
tCK tCH tCL
CKE
COMMAND5
NOP6
ACT
NOP6
WRITE2
NOP6
NOP6
NOP6
NOP6
NOP6
NOP6
NOP6
PRE
AL=1 ADDRESS
RA Col n
WL=2
ALL BANKS
A10
RA
3
ONE BANK
BA0, BA1
Bank x tRCD tRAS
Bank x
Bank x4
tWR9 tRP A
tDQSS (NOM)
DQS, DQS#
tWPRE tDQSL tDQSH tWPST
DQ1 DM
DI n
TRANSITIONING DATA
DON'T CARE
NOTE:
1. 2. 3. 4. 5. 6. 7. 8. 9.
DI n = data-in from column n; subsequent elements are applied in the programmed order. Burst length = 4, AL = 1, and WL = 2 in the case shown. Disable auto precharge. "Don't Care" if A10 is HIGH at T8. PRE = PRECHARGE, ACT = ACTIVE, RA = row address, BA = bank address. NOP commands are shown for ease of illustration; other commands may be valid at these times. tDSH is applicable during tDQSS (MIN) and is referenced from CK T6 or T7. tDSS is applicable during tDQSS (MAX) and is referenced from CK T7 or T8. t WR starts at the end of the data burst regardless of the data mask condition.
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Figure 41: Data Input Timing
T0 CK# CK tDQSS(nominal) DQS# DQS tWPRE DQ DM DI tDSH1 tDSS2 tDSH1 tDSS2 T1 T1n T2 T2n T3 T3n T4
tDQSL tDQSH tWPST
TRANSITIONING DATA
NOTE:
DON'T CARE
1. 2. 3. 4. 5.
tDSH tDSS
(MIN) generally occurs during tDQSS (MIN). (MIN) generally occurs during tDQSS (MAX). WRITE command issued at T0. For x16, LDQS controls the lower byte and UDQS controls the upper byte. WRITE command with WL=2 (CL=3, AL=0) issued at T0.
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Precharge PRECHARGE Command
The PRECHARGE command, illustrated in Figure 42, is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row activation a specified time (tRP) after the precharge command is issued, except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging.
Figure 42: PRECHARGE Command
CK# CK CKE CS# HIGH
RAS#
CAS#
WE#
ADDRESS
ALL BANKS
PRECHARGE Operation
Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA1-BA0 select the bank. Otherwise BA1-BA0 are treated as "Don't Care." When all banks are to be precharged, inputs BA1BA0 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. tRPA timing applies when the PRECHARGE(ALL) command is issued, regardless of the number of banks already open or closed. If a singlebank PRECHARGE command is issued, tRP timing applies.
A10
ONE BANK
BA0, BA1
BA
BA = bank address (if A10 is LOW; otherwise "Don't Care") DON'T CARE
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Self Refresh SELF REFRESH Command
The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR2 SDRAM retains data without external clocking. All power supply inputs (including VREF ) must be maintained at valid levels upon entry/exit AND during self refresh operation. The SELF REFRESH command is initiated like a REFRESH command except CKE is (LOW). The DLL is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh (200 clock cycles must then occur before a READ command can be issued). Clock should remain stable and meeting tCKE specifications at least 1 x tCK after entering self refresh mode. All command and address input signals except CKE are "Don't Care" during self refresh. The procedure for exiting self refresh requires a sequence of commands. First, CK, CK# must be stable and meeting tCK specifications at least 1 x tCK prior to CKE going back HIGH. Once CKE is HIGH (tCKE(min) has been satified with four clock registrations), the DDR2 SDRAM must have NOP or DESELECT commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOP or DESELECT commands for 200 clock cycles before applying any other command.
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Figure 43: Self Refresh
T0 CK# CK1
tCH tCL
T1
T2
Ta0
Ta1
Ta2
Tb0
Tc0
Td0
tCK1 CKE1
tCK1
tISXR6
tCKE (MIN)10
COMMAND5
NOP
REF
NOP7
NOP7
VALID3 8
VALID3 8
ODT8
tAOFD / tAOFPD8 VALID4
ADDRESS
VALID
DQS#, DQS
DQ
DM
tRP2 tCKE
(MIN)9
tXSNR3,6 tXSRD4,6
Enter Self Refresh Mode (synchronous)
Exit Self Refresh Mode (asynchronous)
DON'T CARE
Indicates a break in time scale
NOTE:
1. Clock must be stable and meeting tCK specifications at least 1 x tCK after entering self refresh and at least 1 x tCK prior to exiting self refresh mode. 2. Device must be in the all banks idle state prior to entering self refresh mode. 3. tXSNR is required before any non-READ command can be applied. 4. tXSRD (200 cycles of CK) is required before a READ command can be applied at state Td0. 5. REF = REFRESH command. 6. Self Refresh exit is asynchronous, however, tXSNR and tXSRD timing starts at the first rising clock edge where CKE HIGH satisfies tISXR. 7. NOP or DESELECT commands are required prior to exiting SELF REFRESH until state Tc0, which allows any non-READ command. 8. ODT must be disabled and RTT off (tAOFD and tAOFPD have been satisfied) prior to entering Self Refresh at state T1. 9. Once Self Refresh has been entered tCKE(min) must be satisfied prior to exiting self refresh. 10. CKE must stay high; tCKE(min) High = 3 clock registrations.
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REFRESH REFRESH Command
REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to CAS#-BEFORERAS# (CBR) refresh. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a "Don't Care" during an REFRESH command. The 256Mb DDR2 SDRAM requires REFRESH cycles at an average interval of 7.8125s (maximum). To allow for improved effiT0 CK# CK
tCK tCH tCL
ciency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight REFRESH commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between any REFRESH command and the next REFRESH command is 9 x 7.8125s (70.3s). The REFRESH period begins when the REFRESH command is registered and ends t RFC (min) later.
Figure 44: Refresh Mode
T1 T2 T3 T4 Ta0 Ta1 Tb0 Tb1 Tb2
CKE
COMMAND1
NOP 2
PRE
NOP2
NOP2
REF
NOP2
REF5
NOP2
NOP2
ACT
ADDRESS
ALL BANKS
RA
A101
ONE BANK
RA
BANK1
Bank(s)3
BA
DQS, DQS#4
DQ4
NOTE:
1. PRE = PRECHARGE, ACT = ACTIVE, AR = REFRESH, RA = row address, BA = bank address. 2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active during clock positive transitions. 3. "Don't Care" if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all active banks). 4. DM, DQ, and DQS signals are all "Don't Care"/High-Z for operations shown. 5. The second REFRESH is not required and is only shown as an example of two back-to-back REFRESH commands.
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Power-Down Mode
DDR2 SDRAMs support multiple power-down modes that allow a significant power savings over normal operating modes. The CKE input pin is used to enter and exit different power-down modes. Powerdown entry and exit timings are shown in Figure 45. Detailed power-down entry conditions are shown in Figure 46 through Figure 53. The Truth Table for CKE is shown in Table 9 on page 60 for DDR2 SDRAM. DDR2 SDRAMs require CKE to be registered high (active) at all times that an access is in progress: from the issuing of a READ or WRITE command until completion of the burst. Thus a clock suspend is not supported. For READs, a burst completion is defined when the read postamble is satisfied; for WRITEs, a burst completion is defined when the write postamble and t WR or tWTR are satisfied, and shown in Figure 48 and Figure 49. tWTR is defined as Min(2 or tWTR/tCK rounded up to the next integer). Power-down in Figure 45, is entered when CKE is registered LOW coincident with a NOP or DESELECT command. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down. If power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK#, ODT, and CKE. For maximum power savings, the DLL is frozen during precharge power-down. Exiting active power-down requires the device to be at the same voltage and frequency as when it entered power-down. Exiting precharge power-down requires the device to be at the same voltage as when it entered power-down; however, the clock frequency is allowed to change (See "Precharge Power-Down Clock Frequency Change" on page 7.) The maximum duration for either active or precharge power-down is limited by the refresh requirements of the device tRFC (MAX). The minimum duration for power-down entry and exit is limited by t CKE(min) parameter. While in power-down mode, CKE LOW, a stable clock signal, and stable power supply signals must be maintained at the inputs of the DDR2 SDRAM, while all other input signals are "Don't Care" except ODT. Detailed ODT timing diagrams for different power-down modes are shown for Figure 3 on page 10 through Figure 8 on page 15. The power-down state is synchronously exited when CKE is registered HIGH (in conjunction with a NOP or DESELECT command) as shown in Figure 45.
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Figure 45: Power-Down
T1 CK# CK
tCK VALID1 tCH tCL
T2
T3
T4
T5
T6
T7
T8
COMMAND
NOP tCKE (MIN)3
NOP
NOP
VALID
VALID
CKE
tIH tIH tIS tCKE (MIN)3 VALID tXP4, tXPRD5 tXARD6, tXARDS7 VALID
ADDRESS
VALID
DQS, DQS#
DQ
DM
Enter Power-Down Mode2
Exit Power-Down Mode
DON'T CARE
NOTE:
1. If this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is precharge power-down. If this command is an ACTIVE (or if at least one row is already active), then the power-down mode shown is active power-down. 2. No column accesses are allowed to be in progress at the time power-down is entered. 3. tCKE (MIN) of 3 clocks means CKE must be registered on three consecutive positve clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not trainsition from its valid level during the time period of tIS + 2 * tCK + tIH. CKE must not transition during its tIS and tIH window. 4. tXP timing is used for exit precharge power-down and active power-down to any non-READ command. 5. tXPRD timing is used for exit precharge power-down to any READ command 6. tXARD timing is used for exit active power-down to READ command if 'fast exit' is selected via MR (bit 12 = 0). 7. tXARDS timing is used for exit active power-down to READ command if 'slow exit' is selected via MR (bit 12 = 1).
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Table 9:
Notes 1-3, 12 CKE CURRENT STATE Power Down Self Refresh Bank(s) Active All Banks Idle PREVIOUS CYCLE (n-1) L L L L H H H H CURRENT CYCLE (n) L H L H L L L H COMMAND (n) CS#,RAS#,CAS#,WE# ACTION (n) NOTES 13, 14 4, 8 14 4, 5, 9 4, 8, 10, 11 4, 8, 10 6, 9, 11 7
CKE Truth Table
X Maintain Power-Down DESELECT or NOP Power-Down Exit X Maintain Self Refresh DESELECT or NOP Self Refresh Exit DESELECT or NOP Active Power-Down Entry DESELECT or NOP Precharge Power-Down Entry REFRESH Self Refresh Entry Refer to Command Truth Table 1 on page 7
NOTE:
CKE (n) is the logic state of CKE at clock edge n; CKE (n-1) was the state of CKE at the previous clock edge. Current state is the state of the DDR2 SDRAM immediately prior to clock edge n. COMMAND (n) is the command registered at clock edge n, and ACTION (n) is a result of COMMAND (N). All states and sequences not shown are illegal or reserved unless explicitely described elsewhere in this document. On self refresh exit, DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read commands may be issued only after tXSRD (200 clocks) is satisfied. 6. Self refresh mode can only be entered from the all banks idle state. 7. Must be a legal command as defined in the Command Truth Table. 8. Valid commands for power-down entry and exit are NOP and DESELECT only. 9. Valid commands for Self Refresh Exit are NOP and DESELECT only. 10. Power-down and self refresh can not be entered while READ or WRITE operations, LOAD MODE operations, or PRECHARGE or REFRESH operations are in progress. See Power-Down and Self Refresh sections for a list of detailed restrictions. 11. Minimum CKE HIGH time is tCKE = 3 x tCK. Minimum CKE low time is tCKE = 3 x tCK. This requires a minimum of 3 clock cycles of registration. 12. The state of on-die termination (ODT) does not affect the states described in this table. The ODT function is not available during self refresh. See ODT section for more details and specific restrictions. 13. Power-down modes do not perform any refresh operations. The duration of power-down mode is therefore limited by the refresh requirements. 14. "X" means "Don't Care" (including floating around VREF) in self refresh and power-down. However, ODT must be driven HIGH or LOW in power-down if the ODT function is enabled via EMR(1).
1. 2. 3. 4. 5.
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Figure 46: READ to Power-Down Entry
CK# CK COMMAND
READ NOP NOP NOP VALID NOP
tCKE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
(MIN)
CKE ADDRESS
VALID
A10 DQS, DQS# DQ RL = 3 Power-Down1 Entry TRANSITIONING DATA DON'T CARE
DOUT DOUT DOUT DOUT
NOTE:
1. Power-down entry may occur after the READ burst completes. 2. In the example shown, READ burst completes at T5; earliest power-down entry is at T6.
Figure 47: READ with Auto Precharge to Power-Down Entry
CK# CK COMMAND
READ NOP NOP NOP VALID VALID NOP
t
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CKE (MIN)
CKE
VALID
ADDRESS A10 DQS, DQS# DQ
DOUT
DOUT
DOUT
DOUT
RL = 3 Power-Down1 Entry TRANSITIONING DATA DON'T CARE
NOTE:
1. Power-down entry may occur 1 x tCK after the internal precharge is issued and may be prior to tRP being satisfied. 2. Timing shown above assumes internal PRECHARGE was issued at T5 or earlier. 3. Refer to READ-to-PRECHARGE section for internal precharge timing details.
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Figure 48: WRITE to Power-Down Entry
CK# CK COMMAND
WRITE NOP NOP NOP VALID VALID VALID1 NOP
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCKE (MIN) CKE
ADDRESS A10 DQS, DQS# DQ
VALID
DOUT
DOUT
DOUT
DOUT
WL = 3 tWTR Power-Down Entry TRANSITIONING DATA DON'T CARE
Figure 49: WRITE with Auto Precharge to Power-Down Entry
CK# CK COMMAND
WRITE NOP NOP NOP VALID VALID VALID2 NOP
tCKE
T0
T1
T2
T3
T4
T5
Ta0
Ta1
Ta2
Ta3
Ta4
(MIN)
CKE
ADDRESS A10 DQS, DQS# DQ
VALID
DOUT
DOUT
DOUT
DOUT
WL = 3 WR1 TRANSITIONING DATA DON'T CARE Indicates a break in time scale Power-Down Entry
NOTE:
1. Write Recovery (WR) is programmed through MR[9,10,11] and represents [tWR (MIN) ns / tCK] rounded up to next integer tCK. 2. Internal PRECHARGE occurs at Ta0 when WR has completed; power-down entry may occur 1 x tCK later at Ta1 prior to tRP being satisfied.
Figure 50: REFRESH command to Power-Down Entry
CK# CK COMMAND
VALID REFRESH NOP
tCKE
T0
T1
T2
T3
T4
T5
T6
(MIN)
CKE 1 x tCK Power-Down1 Entry DON'T CARE
NOTE:
1. The earliest PRECHARGE power-down entry may occur is at T2 which is 1 x tCK after the REFRESH command. Precharge power down entry occurs prior to tRFC (MIN) being satisfied.
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Figure 51: ACTIVE Command to Power-Down Entry
CK# CK COMMAND
VALID ACTIVE NOP
T0
T1
T2
T3
T4
T5
T6
ADDRESS
VALID
tCKE (MIN) CKE 1 tCK Power-Down Entry
1
DON'T CARE
NOTE:
1. The earliest PRECHARGE power-down entry may occur is at T2, which is 1 x tCK after the ACTIVE command. Active power-down entry occurs prior to tRCD (MIN) being satisfied.
Figure 52: PRECHARGE Command to Power-Down Entry
CK# CK COMMAND
VALID PRECHARGE NOP
T0
T1
T2
T3
T4
T5
T6
ADDRESS A10
VALID
ALL BANKS vs SINGLE BANK
tCKE
(MIN)
CKE 1 x tCK Power-Down1 Entry
DON'T CARE
NOTE:
1. The earliest power-down entry may occur is at T2, which is 1 x tCK after the PRECHARGE command. Power-down entry occurs prior to tRP (MIN) being satisfied.
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Figure 53: LOAD MODE Command to Power-Down Entry
CK# CK COMMAND
VALID LM NOP NOP
T0
T1
T2
T3
T4
T5
T6
T7
ADDRESS
VALID3
t
CKE (MIN)
CKE
t
RP2
t
MRD Power-Down1 Entry
DON'T CARE
NOTE:
1. The earliest PRECHARGE power-down entry is at T3, which is after tMRD is satisfied. 2. All banks must be in the precharged state and tRP met prior to issuing LM command. 3. Valid address for LM command includes MR, EMR, EMR(2), and EMR(3) registers.
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Precharge Power-Down Clock Frequency Change
When the DRAM is in precharged power-down mode, on-die termination (ODT) must be turned off and CKE must be at a logic LOW level. A minimum of two clocks must pass after CKE goes LOW before clock frequency may change. The DRAM input clock frequency is allowed to change only within minimum and maximum operating frequencies specified for the particular speed grade. During input clock frequency change, ODT and CKE must be held at stable LOW levels. Once the input clock frequency is changed, new stable clocks must be provided to the DRAM before precharge power-down may be exited and DLL must be RESET via EMR after precharge power-down exit. Depending on the new clock frequency an additional MR command may need to be issued to appropriately set the WR MR[11, 10, 9] register. During the DLL relock period of 200 cycles, ODT must remain off. After the DLL lock time, the DRAM is ready to operate with a new clock frequency.
Figure 54: Input Clock Frequency Change During PRECHARGE Power Down Mode
PREVIOUS CLOCK FREQUENCY T0 CK# CK
tCH tCK tCL tCH tCK tCL
NEW CLOCK FREQUENCY T3 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0
T1
T2
2 x tCK (MIN)2
1 x tCK (MIN)3
tCKE (MIN)4
CKE
tCKE (MIN)4 VALID1 NOP
COMMAND
NOP
NOP
LM
NOP
VALID
ADDR
VALID
DLL RESET
VALID
ODT
tXP
DQS, DQS#
High-Z
DQ
High-Z
DM Enter PRECHARGE Power-Down Mode Frequency Change
Exit PRECHARGE Power-Down Mode
200 x tCK Indicates a break in time scale DON'T CARE
NOTE:
1. If this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is precharge power-down, which is required prior to the clock frequency change. 2. A minimum of 2 x tCK is required after entering PRECHARGE power-down prior to changing clock frequencies. 3. Once the new clock frequency has changed and is stable, a minimum of 1 x tCK is required prior to exiting PRECHARGE power-down. 4. Minimum CKE HIGH time is tCKE = 3 x tCK. Minimum CKE low time is tCKE = 3 x tCK. This requires a minimum of 3 clock cycles of registration.
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RESET Function (CKE LOW Anytime)
DDR2 SDRAM applications may go into a RESET state at any time during normal operation. If an application enters a reset condition, the CKE input pin is used to ensure the DDR2 SDRAM device resumes normal operation after reinitializing. All data will be lost during a reset condition; however, the DDR2 SDRAM device will continue to operate properly if the following conditions outlined in this section are satisfied. The RESET condition defined here assumes all supply voltages (VDD, VDDQ, VDDL, and VREF ) are stable and meet all DC specifications prior to, during, and after the RESET operation. All other input pins of the
T0 CK# CK
tCL tDELAY tCL tCKE(MIN)
DDR2 SDRAM device are a "don't care" during RESET with the exception of CKE. If CKE asynchronously drops LOW during any valid operation (including a READ or WRITE burst), the memory controller must satisfy the timing parameter t DELAY before turning off the clocks. Stable clocks must exist at the CK, CK# inputs of DRAM before CKE is raised HIGH, at which time the normal initialization sequence must occur (See "Initialization" on page 12). The DDR2 SDRAM is now ready for normal operation after the initialization sequence. Figure 55 shows the proper sequence for a RESET condition.
T5
tCK
Figure 55: RESET Condition
T1 T2 T3 T4 Ta0 Tb0
CKE
ODT
COMMAND6
READ
NOP2
READ
NOP2
NOP2
NOP2
PRE
DM7
ADDRESS
Col n
Col n
ALL BANKS
A10
BA0, BA1
Bank a
Bank b
DQS7 DQ7 Rtt
High-Z
(( ))
DOUT DOUT DOUT
High-Z
High-Z
(( )) (( ))
High-Z
High-Z
System RESET Unknown RTT ON DON'T CARE TRANSITIONING DATA Indicates a break in time scale
T = 400ns (MIN)
tRP A
Start of Normal Initialization Sequence
For Initilization timing, see time sequence Ta0 in Figure 10, DDR2 Power-Up and Initialization, on page 13
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ODT Timing
There are two timing categories for ODT, turn-on and turn-off. During active mode (CKE HIGH) and "fast-exit" power-down mode (any row of any bank open, CKE LOW, MR[bit12 = 0]), tAOND, tAON, tAOFD, and tAOF timing parameters are applied as shown in Figure 56 and Table 10 on page 68. During "slow-exit" power-down mode (any row of any bank open, CKE LOW, MR[bit12=1]) and precharge power-down mode (all banks/rows precharged and idle, CKE LOW), t AONPD and tAOFPD timing parameters are applied as shown in Figure 57 and Table 11 on page 69. ODT turn-off timing prior to entering any powerdown mode is determined by the parameter tANPD (MIN) shown in Figure 58. At state T2 the ODT HIGH signal satisfies tANPD (MIN) prior to entering powerdown mode at T5. When tANPD (MIN) is satisfied t AOFD and tAOF timing parameters apply. Figure 58 also shows the example where tANPD (MIN) is NOT satisfied since ODT HIGH does not occur until state T3. When tANPD (MIN) is NOT satisfied, tAOFPD timing parameters apply. ODT turn-on timing prior to entering any powerdown mode is determined by the parameter tANPD shown in Figure 59. At state T2, the ODT HIGH signal satisfies tANPD (MIN) prior to entering power-down mode at T5. When tANPD (MIN) is satisfied tAOND and tAON timing parameters apply. Figure 59 also shows the example where tANPD (MIN) is NOT satisfied since ODT HIGH does not occur until state T3. When tANPD (MIN) is NOT satisfied, tAONPD timing parameters apply. ODT turn-off timing after exiting any power-down mode is determined by the parameter tAXPD (MIN) shown in Figure 60. At state Ta1, the ODT LOW signal satisfies tAXPD (MIN) after exiting power-down mode at state T1. When tAXPD (MIN) is satisfied, tAOFD and t AOF timing parameters apply. Figure 60 also shows the example where tAXPD (MIN) is NOT satisfied since ODT LOW occurs at state Ta0. When tAXPD (MIN) is NOT satisfied, tAOFPD timing parameters apply. ODT turn-on timing after exiting any power-down mode is determined by the parameter tAXPD (MIN) shown in Figure 61. At state Ta1, the ODT HIGH signal satisfies tAXPD (MIN) after exiting power-down mode at state T1. When tAXPD (MIN) is satisfied, tAOND and t AON timing parameters apply. Figure 61 also shows the example where tAXPD (MIN) is NOT satisfied since ODT HIGH occurs at state Ta0. When tAXPD (MIN) is NOT satisfied, tAONPD timing parameters apply.
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Figure 56: ODT Timing for Active or "Fast-Exit" Power-Down Mode
CK# CK T0
tCK
T1
tCH tCL
T2
T3
T4
T5
T6
CMD
VALID
VALID
VALID
VALID
VALID
VALID
VALID
ADDR
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CKE tAOND ODT tAOFD
RTT tAON (MIN) tAON (MAX) tAOF (MAX) tAOF (MIN)
RTT Unknown
RTT On
DON'T CARE
Table 10: ODT Timing for Active and "Fast-Exit" Power-Down Modes
PARAMETER ODT turn-on delay ODT turn-on ODT turn-off delay ODT turn-off SYMBOL
tAOND tAON tAOFD tAOF tAC
MIN 2 (MIN) 2.5 (MIN)
tAC
MAX 2 (MAX) + 1,000 2.5 (MAX) + 600
UNITS
tCK
ps
tCK
tAC
tAC
ps
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Figure 57: ODT timing for "Slow-Exit" or Precharge Power-Down Modes
CK# CK T0
tCK
T1
t
T2 CH
t
T3
T4
T5
T6
T7
CL
CMD
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
ADDR
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CKE
ODT
tAONPD tAONPD
(MAX)
(MIN)
RTT
tAOFPD
(MIN)
t
AOFPD (MAX)
Transitioning RTT
RTT Unknown
RTT On
DON'T CARE
Table 11: ODT timing for "Slow-Exit" and Precharge Power-Down Modes
PARAMETER ODT turn-on (power-down mode) ODT turn-off (power-down mode) SYMBOL
tAONPD tAOFPD tAC tAC
MIN (MIN) + 2,000 (MIN) + 2,000 x tCK
MAX 2 x tCK+tAC (MAX) + 1,000 2.5 +
tAC
UNITS ps ps
(MAX) + 1,000
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Figure 58: ODT "Turn Off" Timings when Entering Power-Down Mode
CK# CK
NOP NOP NOP NOP NOP NOP NOP
T0
T1
T2
T3
T4
T5
T6
tANPD (MIN)
CKE
ODT
tAOFD tAOF (MAX)
RTT tAOF (MIN)
ODT
tAOFPD (MAX)
RTT tAOFPD (MIN)
Transitioning RTT
RTT Unknown
RTT On
DON'T CARE
Table 12: ODT "Turn Off" Timings when Entering Power-Down Mode
PARAMETER ODT turn-off delay ODT turn-off ODT turn-off (power-down mode) ODT to power-down entry latency SYMBOL
tAOFD tAOF tAOFPD tANPD tAC
MIN 2.5
tAC tAC
MAX 2.5 (MAX) + 600
tAC tCK
UNITS
tCK
(MIN) 2.5 x
ps ps
tCK
(MIN) + 2,000 3
+
(MAX) + 1,000
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Figure 59: ODT "Turn-On" Timing when Entering Power-Down Mode
CK# CK
NOP NOP NOP NOP
t
T0
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
ANPD (MIN)
CKE
ODT
t
AOND
t
AON (MAX)
RTT
t
AON (MIN)
ODT
tAONPD
(MAX)
RTT
tAONPD
(MIN)
Transitioning RTT
RTT Unknown
RTT On
DON'T CARE
Table 13: ODT "Turn-On" Timing when Entering Power-Down Mode
PARAMETER ODT turn-on delay ODT turn-on ODT turn-on (power-down mode) ODT to power-down entry latency SYMBOL
tAOND tAON tAONPD tANPD tAC tAC
MIN 2 (MIN) 2x
tAC tCK
MAX 2 (MAX) + 1,000
tAC
UNITS
tCK
ps ps
tCK
(MIN) + 2,000 3
+
(MAX) + 1,000
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Figure 60: ODT "Turn-Off" Timing when Exiting Power-Down Mode
CK# CK COMMAND
NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
T0
T1
T2
T3
T4
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
tAXPD (MIN)
CKE
tCKE (MIN)
ODT
tAOFD tAOF (MAX)
RTT tAOF (MIN)
ODT
tAOFPD (MAX)
RTT tAOFPD (MIN)
Transitioning RTT
RTT Unknown
RTT On
DON'T CARE
Indicates a break in time scale
Table 14: ODT "Turn-Of" Timing when Exiting Power-Down Mode
PARAMETER ODT turn-off delay ODT turn-off ODT turn-off (power-down mode) ODT to power-down exit latency SYMBOL
tAOFD tAOF tAOFPD tAXPD tAC
MIN 2.5
tAC tAC
MAX 2.5 (MAX) + 600 2.5 x tCK + tAC (MAX) + 1,000
UNITS
tCK
(MIN)
ps ps
tCK
(MIN) + 2,000 8
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Figure 61: ODT "Turn On" Timing when Exiting Power-Down Mode
CK# CK COMMAND
NOP NOP NOP NOP
tAXPD
T0
T1
T2
T3
T4
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
NOP
NOP
NOP
NOP
NOP
NOP
NOP
(MIN)
CKE
tCKE (MIN)
ODT
tAOND t
AON (MAX)
RTT
t
AON (MIN)
ODT
tAONPD
(MAX)
RTT
tAONPD
(MIN)
Transitioning RTT
RTT Unknown
RTT On
DON'T CARE
Indicates a break in time scale
Table 15: ODT "Turn On" Timing when Exiting Power-Down Mode
PARAMETER ODT turn-on delay ODT turn-on ODT turn-on (power-down mode) ODT to power-down exit latency SYMBOL
t
MIN 2
t tAC t
MAX 2 AC (MAX) + 1,000 2 x tCK + tAC (MAX) + 1,000
UNITS
t
AOND
t
AON
AC (MIN)
CK ps ps
tAONPD t
AXPD
(MIN) + 2,000 8
t
CK
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Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 16: Absolute Maximum DC Ratings
SYMBOL VDD VDDQ VDDL VIN, VOUT TSTG TC II PARAMETER VDD Supply Voltage Relative to VSS VDDQ Supply Voltage Relative to VSSQ VDDL Supply Voltage Relative to VssL Voltage on any Pin Relative to VSS Storage Temperature (Tcase )1 Operating Temperature (Tcase)1,2 Input Leakage Current Any input 0V <= VIN <= VDD (All other pins not under test = 0V) Output Leakage Current 0V <= VOUT <= VDDQ DQs and ODT are disabled VREF Leakage Current VREF = Valid VREF level MIN -1.0 -0.5 -0.5 -0.5 -55 0 -5 MAX 2.3 2.3 2.3 2.3 100 85 5 UNITS V V V V C C uA
IOZ
-5
5
uA
IVREF
NOTE:
-2
2
uA
1. MAX operating case temperature; TC is measured in the center of the package illustrated in Figure 62. 2. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation.
Figure 62: Example Temperature Test Point Location
Test Point
12.00
14.00
6.00
7.00
4.00 8.00 8.00
4.00
8mm x 12mm "FP" FBGA
8mm x 14mm "FG" FBGA
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AC and DC Operating Conditions Table 17: Recommended DC Operating Conditions (SSTL_18)
All voltages referenced to VSS PARAMETER Supply Voltage VDDL Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system)
NOTE:
SYMBOL VDD VDDL VDDQ VREF(DC) VTT
MIN
NOM
MAX 1.9 1.9 1.9 0.51 X VDDQ VREF(DC) + 40
UNITS NOTES V V V V mV 1, 5 4, 5 4, 5 2 3
1.7 1.8 1.7 1.8 1.7 1.8 0.49 x VDDQ 0.50 x VDDQ VREF(DC) - 40 VREF(DC)
1. VDD and VDDQ must track each other. VDDQ must be less than or equal to VDD. 2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-topeak noise (non-common mode) on VREF may not exceed 1% of the DC value. Peak-to-peak AC noise on VREF may not exceed 2 percent of VREF(DC). This measurement is to be taken at the nearest VREF bypass capacitor. 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 4. VDDQ tracks with VDD; VDDL tracks with VDD. 5. VssQ = VssL = Vss
Table 18: ODT DC Electrical Characteristics
All voltages referenced to VSS PARAMETER RTT effective impedance value for 75 setting EMR (A6, A2) = 0, 1 RTT effective impedance value for 150 setting EMR (A6, A2) = 1, 0 Deviation of VM with respect to VDDQ/2
NOTE:
SYMBOL RTT1(EFF) RTT2(EFF) VM
MIN 60 120 -6%
NOM 75 150
MAX 90 180 6%
UNITS NOTES

%
1 1 2
1. RTT1(EFF) and RTT2(EFF) are determined by applying VIH(AC) and VIL(AC) to pin under test separately, then measure current I(VIH(AC)) and I(VIL(AC)) respectively.
VIH ( AC ) - VIL ( AC ) RTT ( EFF ) = ------------------------------------------------------------I ( VIH ( AC ) ) - I ( VIL ( AC ) ) 2 x VM VM = ----------------- - 1 x 100% VDDQ
2. Measure voltage (VM) at tested pin with no load.
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Input Electrical Characteristics and Operating Conditions Table 19: Input DC Logic Levels
All voltages referenced to VSS PARAMETER Input High (Logic 1) Voltage Input Low (Logic 0) Voltage SYMBOL VIH(DC) VIL(DC) MIN MAX UNITS mV mV NOTES
VREF(DC) + 125 VDDQ + 300 -300 VREF(DC) - 125
Table 20: Input AC Logic Levels
All voltages referenced to VSS PARAMETER Input High (Logic 1) Voltage Input Low (Logic 0) Voltage SYMBOL VIH(AC) VIL(AC) MIN MAX UNITS mV mV NOTES
VREF(DC) + 250 - VREF(DC) - 250
Figure 63: Single-Ended Input Signal Levels
1,150mV VIH (AC)
1,025mV
VIH (DC)
936mV 918mV 900mV 882mV 864mV
VREF + AC Noise VREF + DC Error VREF - DC Error VREF - AC Noise
775mV
VIL (DC)
650mV
VIL (AC)
NOTE:
Numbers in diagram reflect nomimal values.
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Table 21: Differential Input Logic Levels
All voltages referenced to VSS PARAMETER DC Input Signal Voltage DC Differential Input Voltage AC Differential Input Voltage AC Differential Cross-Point Voltage Input Midpoint Voltage
NOTE:
SYMBOL VIN(DC) VID(DC) VID(AC) VIX(AC) VMP(DC)
MIN -300 250 500 0.50 x VDDQ - 175 850
MAX VDDQ + 300 VDDQ + 600 VDDQ + 600 0.50 x VDDQ + 175 950
UNITS mV mV mV mV mV
NOTES 1 2 3 4 5
1. VIN (DC) specifies the allowable DC execution of each input of differential pair such as CK, CK#, DQS, DQS#, LDQS, LDQS#, UDQS, UDQS#, and RDQS, RDQS#. 2. VID (DC) specifies the input differential voltage | VTR - VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS, UDQS, RDQS) level and VCP is the complementary input (such as CK#, DQS#, LDQS#, UDQS#, RDQS#). The minimum value is equal to VIH(DC) - VIL(DC). Differential input signal levels are shown in Figure 64. 3. VID(AC) specifies the input differential voltage | VTR - VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS, UDQS, RDQS) level and VCP is the complementary input (such as CK#, DQS#, LDQS#, UDQS#, RDQS#). The minimum value is equal to VIH(AC) - VIL(AC) from Table 20 on page 76. 4. The typical value of VIX (AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates the voltage at which differential input signals must cross as shown in Figure 64. 5. VMP(DC) specifies the input differential common mode voltage (VTR + VCP)/2 where VTR is the true input (CK, DQS) level and VCP is the complementary input (CK#, DQS#). VMP(DC) is expected to be about 0.5*VDDQ.
Figure 64: Differential Input Signal Levels
2.1 V @ VDDQ=1.8V
TR8 VIN(DC) MAX5
1.075 V 0.9V 0.725 V
X
VMP (DC)
1
VIX (AC)
2
VID (DC) 4 VID (AC)
3
X
CP8
- 0.30V
VIN(DC) MIN5
NOTE:
1. 2. 3. 4. 5. 6. 7. 8.
This provides a minimum of 850mV to a maximum of 950mV and is expected to be VDDQ/2. TR and CP must cross in this region. TR and CP must meet at least VID(DC) min when static and is centered around VMP(DC). TR and CP must have a minimum 500mV peak-to-peak swing. TR and CP may not be more positive than VDDQ + 0.3V or more negative than VSS - 0.3V. For AC operation, all DC clock requirements must also be satisfied. Numbers in diagram reflect nominal values. TR represents the CK, DQS, RDQS, LDQS and UDQS signals; CP represents CK#, DQS#, RDQS#, LDQS# and UDQS# signals.
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Table 22: AC Input Test Conditions
PARAMETER SYMBOL MIN MAX UNITS NOTES
Input setup timing measurement reference level BA1-BA0, A0-A12, CS#, RAS#, CAS#, WE#, ODT, DM, UDM, LDM and CKE Input hold timing measurement reference level BA1-BA0, A0-A12, CS#, RAS#, CAS#, WE#, ODT, DM, UDM, LDM and CKE Input timing measurement reference level (single-ended) DQS for x4x8; UDQS, LDQS for x16 Input timing measurement reference level (differential) CK, CK# for x4,x8,x16 DQS, DQS# for x4,x8; RDQS, RDQS# for x8 UDQS, UDQS#, LDQS, LDQS# for x16
NOTE:
VRS
See Note 2
1, 2,
VRH
See Note3
1, 3,
VREF(DC) VRD
VDDQ*0.49
VDDQ*0.51
V V
1, 4 1, 5, 6
VIX(AC)
1. All voltages referenced to VSS. 2. Input waveform setup timing (tISb) is referenced from the input signal crossing at the VIH(AC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test as shown in Figure 69. 3. Input waveform hold (tIHb) timing is referenced from the input signal crossing at the VIL(DC) level for a rising signal and VIH(DC) for a falling signal applied to the device under test as shown in Figure 69 4. Input waveform setup timing (tDS) and hold timing (tDH) for single-ended data strobe is referenced from the crossing of DQS, UDQS, or LDQS through the VREF level applied to the device under test as shown in Figure 71. 5. Input waveform setup timing (tDS) and hold timing (tDH) when differential data strobe is enabled is referenced from the crosspoint of DQS,DQS# or UDQS,UDQS# or LDQS,LDQS# as shown in Figure 70. 6. Input waveform timing is referenced to the crossing point level (VIX) of two input signals (VTR and VCP) applied to the device under test, where VTR is the "true" input signal and VCP is the "complementary" input signal shown in Figure 72. 7. See "Input Slew Rate Derating" on page 79.
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For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value to the tIS and tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + tIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)MAX. If the actual signal is always earlier than the nominal slew rate line between shaded `VREF(DC) to AC region', use nominal slew rate for derating value (Figure 65 on page 80) If the actual signal is later than the nominal slew rate line anywhere between shaded `VREF(DC) to ac region', the slew rate of a tangent line to the actual signal from the AC level to DC level is used for derating value (Figure 66 on page 80) Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)MAX and the first crossing of VREF(DC). Hold
Input Slew Rate Derating
(tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)MIN and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between shaded `dc to VREF(DC) region', use nominal slew rate for derating value (Figure 67 on page 81) If the actual signal is earlier than the nominal slew rate line anywhere between shaded `dc to VREF(DC) region', the slew rate of a tangent line to the actual signal from the dc level to VREF(DC) level is used for derating value (Figure 68 on page 81) Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC)). For slew rates in between the values listed in Table 23, the derating values may obtained by linear interpolation.
Table 23: Setup and Hold Time Derating Values
CK,CK# DIFFERENTIAL SLEW RATE 2.0 V/NS tIS Command/ Address Slew rate (V/ns) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.25 0.2 0.15 0.1 +187 +179 +167 +150 +125 +83 0 -11 -25 -43 -67 -110 -175 -285 -350 -525 -800 -1450 tIH +94 +89 +83 +75 +45 +21 0 -14 -31 -54 -83 -125 -188 -292 -375 -500 -708 -1125 tIS +217 +209 +197 +180 +155 +113 +30 +19 +5 -13 -37 -80 -145 -255 -320 -495 -770 -1420 1.5 V/NS tIH +124 +119 +113 +105 +75 +51 +30 +16 -1 -24 -53 -95 -158 -262 -345 -470 -678 -1095 tIS +247 +239 +227 +210 +185 +143 +60 +49 +35 +17 -7 -50 -115 -225 -290 -465 -740 -1390 1.0 V/NS tIH +154 +149 +143 +135 +105 +81 +60 +46 +29 +6 -23 -65 -128 -232 -315 -440 -648 -1065 UNITS ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
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Figure 65: Nominal Slew Rate for tIS
CK CK
tIS VDDQ tIH tIS tIH
VIH(ac) min VREF to ac region VIH(dc) min nominal slew rate VREF(dc) nominal slew rate VIL(dc) max VREF to ac region VIL(ac) max
VSS
Delta TF
Setup Slew Rate Falling Signal
Delta TR
Setup Slew Rate Rising Signal
=
VREF(dc) - Vil(ac)max
Delta TF
=
Vih(ac)min - VREF(dc) Delta TR
Figure 66: Tangent Line for tIS
CK CK
tIS VDDQ nominal line VIH(ac) min VREF to ac region VIH(dc) min tangent line VREF(dc) tangent line VIL(dc) max VREF to ac region VIL(ac) max nominal line VSS Delta TR
Setup Slew Rate tangent line[Vih(ac)min - VREF(dc)] = Rising Signal Delta TR
tIH
tIS
tIH
Delta TF
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Figure 67: Nominal Slew Rate for tIH
CK CK
tIS VDDQ tIH tIS tIH
VIH(ac) min
VIH(dc) min dc to VREF region VREF(dc) dc to VREF region VIL(dc) max nominal slew rate nominal slew rate
VIL(ac) max
VSS Delta TR Delta TF
Figure 68: Tangent Line for tIH
CK CK
tIS VDDQ tIH tIS tIH
VIH(ac) min
nominal line
VIH(dc) min dc to VREF region VREF(dc) dc to VREF region VIL(dc) max tangent line nominal line tangent line
VIL(ac) max
VSS Delta TR
Hold Slew Rate Rising Signal
Delta TF
=
tangent line [ VREF(dc) - Vil(dc)max ] Delta TR Hold Slew Rate Falling Signal
=
tangent line [ Vih(dc)min - VREF(dc) ] Delta TF
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Figure 69: AC Input Test Signal Waveform Command/Address pins
CK#
CK
t IS b t IH b t IS b t IH b
Logic Le vels
VDDQ VSWING (MAX) VIH(AC)MIN VIH(DC)MIN VREF (DC) VIL(DC)MAX VIL(AC)MAX VSS Q VREF Levels
t IS a t IH a t IS a t IH a
Figure 70: AC Input Test Signal Waveform for Data with DQS,DQS# (differential)
DQS#
DQS
t DS b t DH b t DS b t DH b
Logic Le vels VDDQ
VSWING (MAX)
VIH(AC)MIN VIH(DC)MIN VREF (DC) VIL(DC)MAX VIL(AC)MAX VSS Q
VREF Levels
t DS a
t DH a
t DS a
t DH a
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Figure 71: AC Input Test Signal Waveform for Data with DQS (single-ended)
VREF
DQS
t DS b t DH b t DS b t DH b
Logic Le vels
VDDQ
VSWING (MAX)
VIH(AC)MIN VIH(DC)MIN VREF (DC) VIL(DC)MAX VIL(AC)MAX VSS Q
VREF Levels
t DS a t DH a t DS a t DH a
Figure 72: AC Input Test Signal Waveform (differential)
VDDQ VTR VSWING Crossing Point
VIX VCP VSSQ
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Power and Ground Clamp Characteristics
Power and ground clamps are provided on the following input-only pins: BA1-BA0, A0-A12, CS#, RAS#, CAS#, WE#, ODT, and CKE.
Table 24: Input Clamp Characteristics
VOLTAGE ACROSS CLAMP (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 MINIMUM POWER CLAMP CURRENT (mA) 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.1 1.0 2.5 4.7 6.8 9.1 11.0 13.5 16.0 18.2 21.0 MINIMUM GROUND CLAMP CURRENT (mA) 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.1 1.0 2.5 4.7 6.8 9.1 11.0 13.5 16.0 18.2 21.0
Figure 73: Input Clamp Characteristics
25.0
Minimum Clamp Current (mA)
20.0 15.0 10.0 5.0 0.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
Voltage Across Clamp (V)
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AC Overshoot/Undershoot Specification Table 25: Address and Control Pins
Applies to BA1-BA0, A0-A12, CS#, RAS#, CAS#, WE#, CKE, ODT SPECIFICATION PARAMETER Maximum peak amplitude allowed for overshoot area (See Figure 74) Maximum peak amplitude allowed for undershoot area (See Figure 75) Maximum overshoot area above VDD (See Figure 74) Maximum undershoot area below VSS (See Figure 75) -5, -5E 0.9V 0.9V 0.75V-ns 0.75V-ns -37E 0.9V 0.9V 0.56V-ns 0.56V-ns
Table 26: Clock, Data, Strobe, and Mask Pins
Applies to DQ0-DQxx, DQS, DQS#, RDQS, RDQS#, UDQS, UDQS#, LDQS, LDQS#, DM, UDM, LDM SPECIFICATION PARAMETER Maximum peak amplitude allowed for overshoot area (See Figure 74) Maximum peak amplitude allowed for undershoot area (See Figure 74) Maximum overshoot area above VDDQ (See Figure 74) Maximum undershoot area below VSSQ (See Figure 75) -5, -5E 0.9V 0.9V 0.38V-ns 0.38V-ns -37E 0.9V 0.9V 0.28V-ns 0.28V-ns
Figure 74: Overshoot
Maximum Amplitude Overshoot Area
Volts (V) VDD/VDDQ VSS/VSSQ Time (ns)
Figure 75: Undershoot
VSS/VSSQ Volts (V)
Undershoot Area Maximum Amplitude
Time (ns)
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Output Electrical Characteristics and Operating Conditions Table 27: Differential AC Output Parameters
PARAMETER AC Differential Cross-Point Voltage AC Differential Voltage Swing
NOTE:
SYMBOL VOX(AC) VSWING
MIN 0.50 x VDDQ - 125 1.0
MAX 0.50 x VDDQ + 125
UNITS mV mV
NOTES 1
1. The typical value of VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VOX (AC) is expected to track variations in VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross.
Figure 76: Differential Output Signal Levels
VDDQ VTR VSWING Crossing Point
VOX VCP VSSQ
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Table 28: Output DC Current Drive
PARAMETER Output Minimum Source DC Current Output Minimum Sink DC Current
NOTE:
SYMBOL IOH IOL
VALUE -13.4 13.4
UNITS mA mA
NOTES 1,3,4 2,3,4
1. For IOH (DC); VDDQ = 1.7V, VOUT = 1420mV. (VOUT - VDDQ)/IOH must be less than 21 for values of VOUT between VDDQ and VDDQ - 280mV. 2. For IOL (DC); VDDQ = 1.7V, VOUT = 280mV. VOUT/IOL must be less than 21 for values of VOUT between 0V and 280mV. 3. The DC value of VREF applied to the receiving device is set to VTT. 4. The values of IOH (DC) and IOL (DC) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure VIH (MIN) plus a noise margin and VIL (MAX) minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point (See output IV curves) along a 21 load line to define a convenient driver current for measurement.
Table 29: Output Characteristics
PARAMETER Output impedance Pull-up and Pull-down mismatch Output slew rate
NOTE:
SYMBOL
MIN 12.6 0 1.5
NOM 18
MAX 23.4 4 5
UNITS
NOTES 1,2 1,2,3 1,4,5
s s
V/ns
1. Absolute specifications: 0C Tcase +85C; VDDQ = +1.8V 0.1V, VDD = +1.8V 0.1V. 2. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT - VDDQ)/IOH must be less than 23.4 for values of VOUT between VDDQ and VDDQ - 280mV. Impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV; VOUT/IOL must be less than 23.4 for values of VOUT between 0V and 280mV. 3. Mismatch is absolute value between pull-up and pull-down, both are measured at same temperature and voltage. 4. Output slew rate for falling and rising edges is measured between VTT - 250mV and VTT + 250mV for single ended signals. For differential signals (e.g. DQS - DQS#) output slew rate is measured between DQS - DQS# = -500mV and DQS# DQS = +500mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device. 5. The absolute value of the slew rate as measured from VIL (DC)MAX to VIH (DC) MIN is equal to or greater than the slew rate as measured from VIL (AC) MAX to VIH (AC) MIN. This is guaranteed by design and characterization.
Figure 77: Output Slew Rate Load
VTT = VDDQ/2 25 Reference Point
Output (VOUT)
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Full Strength Pull-Down Driver Characteristics Figure 78: Full Strength Pull-Down Characteristics
Pull-down Characteristics
120.00 100.00 80.00 Iout (mA) 60.00 40.00 20.00 0.00 0.0 0.5 1.0 Vout (V) 1.5
Table 30: Pulldown Current (mA)
VOLTAGE (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 MINIMUM 0.00 4.3 8.6 12.9 17.2 21.1 24.27 26.01 27.43 28.4 29.16 29.79 30.32 30.79 31.19 31.6 31.93 33.24 32.6 33.02 NOMINAL 0.00 5.63 11.3 16.52 22.19 27.59 32.39 36.45 40.38 44.01 47.01 49.63 51.71 53.32 54.9 56.03 57.07 58.16 59.27 60.35 MAXIMUM 0.00 7.90 15.90 23.80 31.80 39.70 47.70 55.00 62.30 69.40 75.30 80.50 84.60 87.70 90.80 92.90 94.90 97.00 99.10 101.10
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Full Strength Pull-Up Driver Characteristics Figure 79: Full Strength Pull-up Characteristics
Pull-up Characteristics
0.0 0.0 -20.0 -40.0 Iout (mA) -60.0 -80.0 -100.0 -120.0 VDDQ - Vout (V) 0.5 1.0 1.5
Table 31: Pull-Up Current (mA)
VOLTAGE (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 MINIMUM 0.00 -4.3 -8.6 -12.9 -17.2 -21.1 -24.27 -26.01 -27.43 -28.4 -29.16 -29.79 -30.32 -30.79 -31.19 -31.6 -31.93 -33.24 -32.6 -33.02 NOMINAL 0.00 -5.63 -11.3 -16.52 -22.19 -27.59 -32.39 -36.45 -40.38 -44.01 -47.01 -49.63 -51.71 -53.32 -54.9 -56.03 -57.07 -58.16 -59.27 -60.35 MAXIMUM 0.0 -7.9 -15.9 -23.8 -31.8 -39.7 -47.7 -55.0 -62.3 -69.4 -75.3 -80.5 -84.6 -87.7 -90.8 -92.9 -94.9 -97.0 -99.1 -101.1
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FBGA Package Capacitance Table 32: Input Capacitance
PARAMETER Input Capacitance: CK, CK# Delta Input Capacitance: CK, CK# Input Capacitance: BA1-BA0, A0-A12, CS#, RAS#, CAS#, WE#, CKE, ODT Delta Input Capacitance: BA1-BA0, A0-A12, CS#, RAS#, CAS#, WE#, CKE, ODT Input/Output Capacitance: DQs, DQS, DM, NF Delta Input/Output Capacitance: DQs, DQS, DM, NF
NOTE:
SYMBOL CCK CDCK CI CDI CIO CDIO
MIN 1.0 - 1.0 - 2.5 -
MAX 2.0 0.25 2.0 0.25 4.0 0.5
UNITS pF pF pF pF pF pF
NOTES 1 2 1 2 1 3
1. This parameter is sampled. VDD = +1.8V 0.1V, VDDQ = +1.8V 0.1V, VREF = VSS, f = 100 MHz, TCASE = 25C, VOUT (DC) = VDDQ/2, VOUT (peak to peak) = 0.1V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 2. The input capacitance per pin group will not differ by more than this maximum amount for any given device. 3. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device.
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IDD Specifications and Conditions Table 33: DDR2 IDD Specifications and Conditions
Notes: 1-5; notes appear on page 92. PARAMETER/CONDITION Operating one bank active-precharge current; t CK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), t RC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W. Precharge power-down current; All banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Precharge quiet standby current; All banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Precharge standby current; All banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Active power-down current; All banks open; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRAS MAX (IDD), tRP = t RP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING. Burst refresh current; tCK = tCK (IDD); Refresh command at every tRFC (IDD) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING. SYMBOL CONFIG x4, x8 x16 x4, x8 IDD1 x16 90 85 80 -37E 80 80 90 -5E 75 75 85 -5 70 70 80 mA UNITS
IDD0
mA
IDD2P
x4, x8, x16
5
5
5
mA
IDD2Q
x4, x8 x16 x4, x8 x16 Fast PDN Exit MR[12] = 0 Slow PDN Exit MR[12] = 1 x4, x8
35 35 35 35 25 6 40 40
25 25 30 30 20 6 30 30
25 25 30 30 20
mA
IDD2N
mA
IDD3P
mA 6 30 mA 30
IDD3N x16
x4, x8 IDD4W x16 x4, x8 IDD4R x16
160 180 150
125 140 115
125 mA 140 115 mA
160
120
120
x4, x8 IDD5 x16
170 170
165 165
165 mA 165
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Table 33: DDR2 IDD Specifications and Conditions (Continued)
Notes: 1-5; notes appear on page 92. PARAMETER/CONDITION Self refresh current; CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING. Operating bank interleave read current; All bank interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD)-1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC(IDD), t RRD = tRRD(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING; See IDD7 Conditions for detail.
NOTE:
SYMBOL IDD6
CONFIG x4, x8, x16
-37E 5
-5E 5
-5 5
UNITS mA
x4, x8 IDD7 x16
240
230
230 mA
240
230
230
1. IDD specifications are tested after the device is properly initialized. 0C TCASE 85C. VDD = +1.8V 0.1V, VDDQ = +1.8V 0.1V, VDDL= +1.8V 0.1V, VREF=VDDQ/2. 2. Input slew rate is specified by AC Parametric Test Conditions. 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and UDQS#. IDD values must be met with all combinations of EMR bits 10 and 11. 5. Definitions for IDD Conditions: LOW is defined as VIN VIL (AC) (MAX). HIGH is defined as VIN VIH (AC) (MIN). STABLE is defined as inputs stable at a HIGH or LOW level. FLOATING is defined as inputs at VREF = VDDQ/2. SWITCHING is defined as inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals. Switching is defined as inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.
Table 34: General IDD Parameters
IDD PARAMETER CL (IDD)
tRCD tRC
-37E 4 15 60 7.5 10 3.75 45 70,000 15 75
-5E 3 15 55 7.5 10 5 40 70,000 15 75
-5 4 20 65 7.5 10 5 45 70,000 20 75
UNITS
tCK
(IDD)
ns ns ns ns ns ns ns ns ns
(IDD) (IDD) - x4/x8
tRRD t
RRD (IDD) - x16 (IDD)
tCK t
RAS MIN (IDD) MAX (IDD)
tRAS tRP t
(IDD)
RFC (IDD)
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IDD7 Conditions
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification.
Table 35: IDD7 Timing Patterns
All Bank Interleave Read operation SPEED GRADE -5 -5E -37E
NOTE:
IDD7 TIMING PATTERNS FOR x4/x8/x16 A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D D A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
1. 2. 3. 4.
Legend: A = active; RA = read auto precharge; D = deselect. All banks are being interleaved at minimum tRC (IDD) without violating tRRD (IDD) using a burst length of 4. Control and address bus inputs are STABLE during DESELECTs. IOUT = 0mA.
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Table 36: AC Operating Conditions (Sheet 1 of 4)
Notes: 1-5; notes appear on page 98; 0C Tcase +85C; VDDQ = +1.8V 0.1V, VDD = +1.8V 0.1V AC CHARACTERISTICS PARAMETER Clock cycle time Clock CL = 4 CL = 3 SYMBOL
t
-37E MIN 3,750 5,000 0.45 0.45 MIN (tCH, tCL) TBD -500 TBD +500
tAC tAC
-5E MAX 8,000 8,000 0.55 0.55 MIN 5,000 5,000 0.45 0.45 MIN (tCH, tCL) TBD -600 TBD +600
tAC
-5 MAX 8,000 8,000 0.55 0.55 MIN 5,000 - 0.45 0.45 MIN (tCH, tCL) TBD -600 TBD +600
tAC
MAX 8,000 - 0.55 0.55
UNITS ps ps
t
NOTES 16, 25 16, 25 19 19 20 18
CK (4) (3)
t
tCK
CK high-level width CK low-level width Half clock period Clock jitter DQ output access time from CK/CK# Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input hold time relative to DQS DQ and DM input pulse width (for each input) Data hold skew factor DQ-DQS hold, DQS to first DQ to go nonvalid, per access Data valid output window (DVW)
CH
CK
tCL tHP t
tCK
ps ps ps ps ps ps ps ps ps
tCK
JIT
tAC tHZ tLZ tDS
MAX
MAX
MAX
8, 9 8, 10 7, 15, 22 7, 15, 22 7, 15, 22 7, 15, 22
MIN tAC MAX tAC MIN tAC MAX tAC MIN tAC MAX 400 400 150 275 0.35 400 450
tHP t
Vref
350 350 100 225 0.35
400 400 150 275 0.35 450
tHP t
tDH Vref tDS VAC
Data
tDH VDC tDIPW tQHS tQH
ps ps 15, 17
tHP t
QHS -
QHS -
QHS -
tDVW
tQH
tQH
tQH
tDQSQ
tDQSQ
tDQSQ
ns
15, 17
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Table 36: AC Operating Conditions (Sheet 2 of 4)
Notes: 1-5; notes appear on page 98; 0C Tcase +85C; VDDQ = +1.8V 0.1V, VDD = +1.8V 0.1V AC CHARACTERISTICS PARAMETER DQS input high pulse width DQS input low pulse width DQS output access time from CK/CK# DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time DQS-DQ skew, DQS to last DQ valid, per group, per access DQS read preamble DQS read postamble DQS write preamble setup time DQS write preamble DQS write postamble Write command to first DQS latching transition SYMBOL
t
-37E MIN 0.35 0.35 -450 0.2 0.2 300 0.9 0.4 0 0.25 0.4 WL 0.25 0.6 WL + 0.25 1.1 0.6 0.9 0.4 0 0.25 0.4 WL 0.25 +450 MAX MIN 0.35 0.35 -500 0.2 0.2
-5E MAX MIN 0.35 0.35 +500 -500 0.2 0.2 350 1.1 0.6 0.9 0.4 0 0.25 0.6 WL + 0.25 0.4 WL 0.25
-5 MAX UNITS
t t
NOTES
DQSH DQSL
CK CK
t
tDQSCK tDSS tDSH
+500
ps
tCK tCK
Data Strobe
tDQSQ tRPRE tRPST tWPRES tWPRE tWPST tDQSS
350 1.1 0.6
ps
tCK tCK
15, 17
ps
tCK
12, 13
0.6 WL + 0.25
tCK tCK
11
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Table 36: AC Operating Conditions (Sheet 3 of 4)
Notes: 1-5; notes appear on page 98; 0C Tcase +85C; VDDQ = +1.8V 0.1V, VDD = +1.8V 0.1V AC CHARACTERISTICS PARAMETER Address and control input pulse width for each input Address and control input setup time Address and control input hold time Address and control input setup time Address and control input hold time CAS# to CAS# command delay ACTIVE to ACTIVE (same bank) command ACTIVE bank a to ACTIVE bank b command Command and Address ACTIVE to READ or WRITE delay Four Bank Activate period Four Bank Activate period ACTIVE to PRECHARGE command Internal READ to precharge command delay Write recovery time Auto precharge write recovery + precharge time Internal WRITE to READ command delay PRECHARGE command period PRECHARGE ALL command period LOAD MODE command cycle time CKE low to CK,CK# uncertainty SYMBOL
t
-37E MIN 0.6 500 500 250 375 2 60 7.5 10 15 37.5 50 45 7.5 15
tWR tRP
-5E MAX MIN 0.6 600 600 350 475 2 60 7.5 10 15 37.5 50 MAX MIN 0.6 600 600 350 475 2 65 7.5 10 20 37.5 50 70,000 45 7.5 15 +
tWR tRP
-5 MAX UNITS
t
NOTES
IPW ISa
CK 6, 22 6, 22 6, 22 6, 22
t t
IHa
tIS b tIH b tCCD tRC tRRD (x4, x8) tRRD
tCK
ns ns ns ns ns ns 70,000 ns ns ns + ns ns ns ns
tCK
34 28 28
(x16)
tRCD tFAW
(x4, x8)
tFAW
31 31 21, 34 24, 28 28 23 28 32 32
(x16)
tRAS
70,000
40 7.5 15
t
RTP
tWR tDAL t
+
tWR tRP
WTR
tRP
7.5 15
tRP
10 15
tRP
10 20
tRP t
tRPA tMRD tDELAY
+ t CK 2
+ t CK 2
+ CK 2
4.375
4.375
5.83
5.83
5.83
5.83
ns
29
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256Mb: x4, x8, x16 DDR2 SDRAM
Table 36: AC Operating Conditions (Sheet 4 of 4)
Notes: 1-5; notes appear on page 98; 0C Tcase +85C; VDDQ = +1.8V 0.1V, VDD = +1.8V 0.1V AC CHARACTERISTICS PARAMETER Refresh REFRESH to Active or Refresh to Refresh command interval Average periodic refresh interval Self Refresh Exit self refresh to nonREAD command Exit self refresh to READ command Exit self refresh timing reference ODT turn-on delay ODT turn-on ODT turn-off delay ODT turn-off SYMBOL
t
-37E MIN 75 MAX 70,000 MIN 75
-5E MAX 70,000 MIN 75
-5 MAX 70,000 UNITS ns NOTES 14
RFC
t
REFI
tRFC
7.8
tRFC
7.8
tRFC
7.8
s ns
t
14
tXSNR
(MIN) + 10 200 250 2
tAC (MIN)
(MIN) + 10 200 350 2
tAC
(MIN) + 10 200 350 2
tAC
t
XSRD
CK 6, 30
tISXR tAOND tAON tAOFD tAOF
ps 2
tAC tCK
2
tAC (MIN)
2
tAC (MIN)
(MAX) + 1,000 2.5
tAC (MAX) + 600
(MAX) + 1000 2.5
tAC (MAX) + 600
(MAX) + 1000 2.5
tAC (MAX) + 600
ps
tCK
26
2.5
tAC
2.5
tAC
2.5
tAC
(MIN)
tAC
(MIN)
tAC
(MIN)
tAC
ps
27
ODT turn-on (powerdown mode)
tAONPD
(MIN) + 2000
tAC
2 x tCK + tAC (MAX) + 1,000 2.5 x tCK + tAC (MAX) + 1,000
(MIN) + 2,000
tAC
2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1,000
(MIN) + 2,000
tAC
2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1,000
ODT
ps
ODT turn-off (powerdown mode) ODT to power-down entry latency ODT power-down exit latency Exit active power-down to READ command, MR[bit12=0] Exit active power-down to READ command, MR[bit12=1] Exit precharge powerdown to any non-READ command. Exit precharge powerdown to READ command. CKE minimum high/low time
tAOFPD
(MIN) + 2,000 3 8 2
(MIN) + 2,000 3 8 2
(MIN) + 2,000 3 8 2
ps
tANPD t
tCK t
AXPD
CK
t
XARD
tCK
Power-Down
t
XARDS
6 - AL
6 - AL
6 - AL
t
CK
tXP
2 6 - AL 3
2 6 - AL 3
2 6 - AL 3
tCK
t
XPRD
tCKE
t
CK 35
tCK
09005aef80b12a05 256Mb_DDR2_2.fm - Rev. C 5/04 EN
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256Mb: x4, x8, x16 DDR2 SDRAM
Notes
1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load:
VTT = VDDQ/2 25 Reference Point
8.
Output (VOUT)
9.
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.0V in the test environment and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1.0V/ns for signals in the range between VIL (AC) and VIH (AC). Slew rates less than 1.0V/ns require the timing parameters to be derated as specified. 5. The AC and DC input level specifications are as defined in the SSTL_18 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. Command/Address minimum input slew rate is at 1.0V/ns. Command/Address input timing needs to be derated if the slew rate is less than 1.0V/ns. This is easily accommodated using tISb and the Setup and Hold Time Derating Values table. tIS timing (tISb) is referenced from VIH(AC) for a rising signal and VIL(AC) for a falling signal. tIH timing (tIHb) is referenced from VIH(AC) for a rising signal and VIL(DC) for a falling signal. The timing table also lists the tISb and tIHb values for a 1.0V/ns slew rate; these are the "base" values. 7. Data minimum input slew rate is at 1.0V/ns. Data input timing needs to be derated if the slew rate is less than 1.0V/ns. This is easily accommodated if the timing is referenced from the logic trip points. t DS timing (tDSVAC) is referenced from VIH(AC) for a rising signal and VIL(AC) for a falling signal. tIH timing (tIHVDC) is referenced from VIH(DC) for a rising signal and VIL(DC) for a falling signal. The timing table also lists the tDSb (tIHVDC)and tDHb (tDSVAC) values for a 1.0V/ns slew rate. If the DQS/DQS# differential strobe feature is not enabled, timing is no longer referenced to the
10. 11.
12.
13.
14.
15.
16. 17.
18.
crosspoint of DQS/DQS#. Data timing is now referenced to VREF, provided the DQS slew rate is not less than 1.0V/ns. If the DQS slew rate is less than 1.0V/ns, then data timing is now referenced to VIH(AC) for a rising DQS and VIL(DC) for a falling DQS. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (tHZ) or begins driving (tLZ). This maximum value is derived from the referenced test load. tHZ (MAX) will prevail over t DQSCK (MAX) + tRPST (MAX) condition. t LZ (MIN) will prevail over a tDQSCK (MIN) + t RPRE (MAX) condition. The intent of the Don't Care state after completion of the postamble is the DQS-driven signal should either be high, low or High-Z and that any signal transition within the input switching region must follow valid input requirements. That is if DQS transitions high (above VIHDC(min) then it must not transition low (below VIH(DC) prior to t DQSH(min). This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. The refresh period is 64ms. This equates to an average refresh rate of 7.8125s. However, a REFRESH command must be asserted at least once every 70.3s or tRFC (MAX). To ensure all rows of all banks are properly refreshed, 8192 REFRESH commands must be issued every 64ms. Referenced to each output group: x4 = DQS with DQ0-DQ3; x8 = DQS with DQ0-DQ7; x16 = LDQS with DQ0-DQ7; and UDQS with DQ8-DQ15. CK and CK# input slew rate must be 1V/ns ( 2 V/ns if measured differentially). The data valid window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and . t QH(tQH=tHP-tQHS). The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. t JIT specification is currently TBD.
09005aef80b12a05 256Mb_DDR2_2.fm - Rev. C 5/04 EN
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256Mb: x4, x8, x16 DDR2 SDRAM
19. MIN(tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. This value can be greater than the minimum specification limits for t CL and tCH). For example, tCL and tCH are = 50 percent of the period, less the half period jitter [tJIT(HP)] of the clock source, and less the half period jitter due to cross talk [tJIT(cross talk)] into the clock traces. 20. tHP (MIN) is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs. 21. READs and WRITEs with auto precharge are allowed to be issued before tRAS (MIN) is satisfied since tRAS lockout feature is supported in DDR2 SDRAM. 22. VIL/VIH DDR2 overshoot/undershoot. See "AC Overshoot/Undershoot Specification" on page 86. 23. tDAL = (nWR) + (tRP/tCK): For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the application clock period; nWR refers to the tWR parameter stored in the MR[11,10,9]. Example: For -37E at tCK = 3.75 ns with tWR programmed to four clocks. tDAL = 4 + (15 ns/3.75 ns) clocks = 4 +(4) clocks = 8 clocks. 24. The minimum READ to internal PRECHARGE time. This parameter is only applicable when t RTP/(2*tCK) > 1. If tRTP/(2*tCK) 1, then equation AL + BL/2 applies. Notwithstanding, tRAS (MIN) has to be satisfied as well. The DDR2 SDRAM will automatically delay the internal PRECHARGE command until tRAS (MIN) has been satisfied. 25. Operating frequency is only allowed to change during self refresh mode (See "Self Refresh" on page 34), precharge power-down mode (See "Power-Down Mode" on page 37), and system reset condition (see "RESET Function (CKE LOW Anytime)" on page 8. 26. ODT turn-on time tAON (MIN) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn-on time tAON (MAX) is when the ODT resistance is fully on. Both are measured from tAOND. ODT turn-off time tAOF (MIN) is when the device starts to turn off ODT resistance. ODT turn off time tAOF (MAX) is when the bus is in high impedance. Both are measured from tAOFD. This parameter has a two clock minimum requirement at any tCK. t DELAY is calculated from tIS + tCK + tIH so that CKE registration LOW is guaranteed prior to CK, CK# being removed in a system RESET condition. "RESET Function (CKE LOW Anytime)" on page 8. t ISXR is equal to tIS and is used for CKE setup time during self refresh exit shown in Figure 31 on page 36. No more than 4 bank ACTIVE commands may be issued in a given tFAW(min) period. tRRD(min) restriction still applies. The tFAW(min) parameter applies to all 8 bank DDR2 devices, regardless of the number of banks already open or closed. tRPA timing applies when the PRECHARGE(ALL) command is issued, regardless of the number of banks already open or closed. If a single-bank PRECHARGE command is issued, tRP timing applies. tRPA(min) applies to all 8-bank DDR2 devices. Value is minimum pulse width, not the number of clock registrations. Applicable to Read cycles only. Write cycles generally require additional time due to Write recovery time (tWR) during auto precharge. t CKE (MIN) of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 * tCK + tIH.
27.
28. 29.
30.
31.
32.
33. 34.
35.
09005aef80b12a05 256Mb_DDR2_2.fm - Rev. C 5/04 EN
99
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.
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256Mb: x4, x8, x16 DDR2 SDRAM
Figure 80: Package Drawing 60-Ball (8mmx12mm) FBGA
0.850 0.05 0.155 0.013 SEATING PLANE C 1.80 0.05 CTR 6.40 60X 0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PREREFLOW DIAMETER IS O 0.42 BALL A9 0.80 TYP 8.00 C L 12.00 0.10 0.80 TYP BALL A1 ID BALL A1 SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR 95.5% Sn, 3% Ag, 0.5% Cu SOLDER BALL PAD: O .33mm SUBSTRATE: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC BALL A1 ID
0.10 C
4.00 0.05 6.00 0.05
C L 3.20 0.05 4.00 0.05 1.3 MAX
8.00 0.10
NOTE:
All dimensions are in millimeters.
09005aef80b12a05 256Mb_DDR2_2.fm - Rev. C 5/04 EN
100
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.
www..com
256Mb: x4, x8, x16 DDR2 SDRAM
Figure 81: Package Drawing 84-Ball (8mmx14mm) FBGA
0.850 0.05 0.155 0.013 SEATING PLANE C 0.10 C
1.80 0.05 CTR
6.40
SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag or 96.5% Sn, 3% Ag, 0.5% Cu SOLDER BALL PAD: O 0.33mm SUBSTRATE: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC
BALL A1 ID BALL #1 ID
84X O0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PREREFLOW DIAMETER IS O0.42
BALL A9
0.80 TYP
BALL A1 7.00 0.05
11.20
C L 0.80 TYP 5.60 0.05 14.00 0.10
C L 3.20 0.05 4.00 0.05 8.00 0.10 1.3 MAX
NOTE:
All dimensions are in millimeters.
Data Sheet Designation
Preliminary: Initial characterization limits, subject to change upon full characterization of production devices.
(R)
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
09005aef80b12a05 256Mb_DDR2_2.fm - Rev. C 5/04 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.
101


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